Fairchild Semiconductor Corporation

Jim Wunderlich

Ronald B Hulfachor

James J McDonald, Ii

A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.

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Cape Elizabeth, ME, United States of America

Jim Wunderlich