Harris Corporation

Jim Snell

Carl F Andren

Leonard V Lucas

John Christ Fakatselis

Perry W Frogge

Al Petrick

Ravindra V Gokhale

A digital data radio receiver and method evaluates a data signal preamble received on an antenna to determine whether the antenna should receive the data signal following the preamble. The receiver determines frequency offsets from a desired frequency for each symbol in a block of symbols in the preamble, determines the variance of the frequency offsets, determines the average magnitude of the symbols in the block of symbols, where the determination of average magnitude may be performed in parallel with the determination of variance of the frequency offsets, and evaluates the variance and the average magnitude for the block of symbols to determine whether the preamble is actually noise and to assess reception quality at the antenna. In a two antenna diversity receiver system, these steps may be performed first on a block of symbols received at one antenna and then performed on the next block of symbols received at another antenna. This provides two evaluations that may be compared to select the antenna with the best reception.

Short burst acquisition circuit and method for direct sequence spread

A method of estimating signal quality in a radio demodulator receiving an input stream of symbols includes the steps of sampling a phase-only portion of each of the symbols in the input stream, determining a phase error for each of the samples of the phase-only portions, and calculating a signal quality estimate from a plurality of the sample phase errors. The signal quality estimate may be an average magnitude of a predetermined number of sample phase errors. The input stream may be symbols in the preamble, or symbols in the data signal that follows.

Method of estimating signal quality in a DPSK demodulator

A direct sequence spread spectrum receiver and method for acquiring radio-frequency signals is provided for acquiring data from signals which have been transmitted in a spread spectrum system. The receiver is capable of receiving short data bursts from transmitters without prior knowledge of the time or location of the transmission and rapidly acquiring the signal before continuing with reliable data demodulation. The system includes one or more antennae for receiving RF signals which may be selectively connected to provide the received signals to the system for processing, a quadrature demodulator for providing I and Q baseband signals to a digital baseband processor which includes A/D converters, dual correlators for despreading the digital I and Q signals, a cartesian to polar converter, a demodulator for demodulating the polar coordinate digital I and Q signals, and a data descrambler for obtaining a serial data stream which may be provided to a serial interface.

Short burst direct acquisition direct sequence spread spectrum receiver

A method and circuit for controlling a reference voltage for an analog-to-digital converter having plural outputs includes a sensor for indicating when outputs from the A/D converter are at least a desired voltage, and a processor responsive to the sensor and connected to a digital-to-analog converter which provides a reference voltage for the A/D converter. The processor provides signals to the D/A converter which change the reference voltage. A logic unit in the processor increments an accumulator when either an I or a Q component in the A/D converter output is at least the desired voltage and decrements the accumulator when neither the I nor the Q component is at least the desired voltage. A counter may buffer the accumulator changes by using only several of the most significant bits of the counter to change the A/D converter reference voltage.

A/D reference level adjustment circuit to maintain optimum dynamic range

In a direct sequence spread spectrum receiver, an apparatus for obtaining and adjusting bit synchronization. In one aspect, the bit synchronization is adjusted by selectively inverting a clocking circuit to delay sampling by one-half a clock cycle and to combine the inversion with a skipping of one cycle to advance the sampling by one-half cycle. In another aspect of the invention, the synchronization circuit avoids overflow of accumulating components by downshifting both the partial sums and the input data when needed.

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Palm Bay, FL, United States of America

Jim Snell