Globalfoundries Inc.

International Business Machines Corporation

Jim Shih-Chun Liang

Baozhen Li

Chih-Chao Yang

Atsushi Ogino

Keith Kwong Hon Wong

Naftali Eliahu Lustig

Wei-Tsu Tseng

Joyeeta Nag

Domingo A Ferrer

Michael Patrick Chudzik

Andrew Herbert Simon

George Stojan Tulevski

Kathryn Turner Schonenberg

Ning Lu

Ernest Y Wu

Tian Shen

Shahrukh Akbar Khan

Nan Jing

Justin C Long

Domingo A Ferrer Luppi

An integrated circuit structure is provided. The integrated circuit structure includes a back end of line (BEOL) wiring layer including metal lines and a first area between the metal lines. The integrated circuit structure also includes a metal-insulator-metal (MIM) capacitor formed in the first area. The MIM capacitor includes a first electrode, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, a second dielectric layer formed on the second electrode, a third electrode formed on the second dielectric layer, a third dielectric layer formed on the third electrode, a fourth electrode formed on the third dielectric layer, a first metal interconnect electrically connecting the first electrode and the third electrode, and a second metal interconnect electrically connecting the second electrode to the fourth electrode.

MIM capacitor structures

A metal insulator metal capacitor and method for fabricating a metal insulator metal capacitor (MIMcap) are disclosed. A first level metal pattern is embedded in a first dielectric layer over a substrate. The first level metal pattern has a top surface co-planar with a top surface of the first dielectric layer. In a selected etch step, either one of the first metal pattern or the first dielectric is etched to form a stepped top surface. A conformal insulating layer on the stepped top surface. The MIMcap is formed on the conformal insulating layer in a conformal manner.

High performance metal insulator metal capacitor

Metal e-fuse structure formed during back-end-of-line during processing and integral with on-chip metal-insulator-metal (MIM) capacitor (MIMcap). The metal e-fuse structures are extensions of MIMcap electrodes and are structured to isolate BEOL MIM capacitors for trimming and/or to isolate shorted or rendered highly leaky due to in process, or service induced defects. In one embodiment, the method incorporates the integral, co-processed metal e-fuse in series between the MIM capacitor and an active circuit. When a high current passes through the e-fuse element, the e-fuse element is rendered highly resistive or electrically open thereby disconnecting the MIM capacitor or electrode plate from the active circuitry. The e-fuse structure may comprise a thin neck portion(s) or zig-zag neck portion that extend from an MIMcap electrode away from the MIMcap between two inter-level interconnect via structures.

E-fuse co-processed with MIM capacitor

An IC device includes a simultaneously formed capacitor and resistor structure. The capacitor and resistor may be located between a Back End of the Line (BEOL) interconnect stack and an external device interconnect pad of the IC device. The resistor may be used to step down a voltage applied across the resistor. The resistor may include one or more resistor plates that are formed simultaneously with a respective one or more plates of the capacitor. For example, a capacitor plate and a resistor plate may be patterned and formed from the same conductive sheet. Each of the resistor plates may be connected to one or more vertical interconnect accesses (VIA).

On integrated circuit (IC) device simultaneously formed capacitor and resistor

An IC device includes an integrated capacitor and anti-fuse. Prior to programming of the anti-fuse, electrical current is configured to flow siloed between a first circuit element and a second circuit element through a first VIA. The anti-fuse may be programed by applying a fusing voltage to a second VIA to charge an anti-fuse plate. Within the anti-fuse, the anti-fuse plate is separated from the first capacitor plate by a dielectric. The fusing voltage causes an electric field between the plates to exceed a breakdown field strength of the dielectric which results in an electric arc between the anti-fuse plate and the capacitor plate. The electric arc fuses or otherwise joins the anti-fuse plate and the capacitor plate. Functionality of the IC device may be altered by allowing or driving current from the first circuit element or the second circuit element across the fused plates.

Integrated circuit (IC) device integral capacitor and anti-fuse

An eFuse structure including a semiconductor substrate; back end of the line (BEOL) metallization levels on the semiconductor substrate; vias extending through the metallization levels; at least one of the metallization levels including one or more metallic plates in electrical contact with one of the vias, the one or more metallic plates having at least one fusible link in electrical contact with one or more additional vias. The eFuse structure may form a multi-fuse structure such that each fusible link may be fused separately or together at the same time.

EFuse structure with multiple links

An IC device, such as a wafer, chip, die, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like include a chamfered VIA that connects an upper wiring line and a first lower wiring line. The chamfered VIA includes a chamfer or fillet upon the edge that connects the VIA sidewall(s) with the VIA contact surface that is connected to the first lower wiring line. The chamfer or fillet effectively increases the amount of a dielectric material, such as a high-k dielectric material, within a trench of the VIA and that is between the chamfered VIA and a second lower wiring line that neighbors the first lower wiring line. This increased dielectric material improves TDDB between the chamfered VIA and the second lower wiring line and mitigates TDDB effects, such as electrical shorts between the chamfered VIA and the second lower wiring line.

Back end of line (BEOL) time dependent dielectric breakdown (TDDB) mitigation within a vertical interconnect access (VIA) level of an integrated circuit (IC) device

The present disclosure relates to semiconductor structures and, more particularly, to contact and interconnect structures and methods of manufacture. The structure includes: a single damascene contact structure in electrical contact with a contact of a source region or drain region; and a single damascene interconnect structure in a wiring layer and in direct electrical contact with the single damascene contact structure.

Contact and interconnect structures

Aspects of the present disclosure include a method for forming a contact on a semiconductor device, the semiconductor device including a conductive region disposed over a substrate, the method comprising: depositing a dielectric material on the substrate; forming an opening in the dielectric material to expose the conductive region; forming a barrier layer on a lower surface and sidewalls of the opening in the dielectric material, the barrier layer terminating below an upper surface of the dielectric material and surrounding a lower portion of the opening; depositing cobalt in the lower portion of the opening, the cobalt terminating at an upper surface of the barrier layer; depositing tungsten to fill the opening to at least the upper surface of the dielectric material; and planarizing the upper surface of the dielectric material with the tungsten in the opening.

Method to form interconnect structure with tungsten fill

A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.

Method to reduce resistance for a copper (Cu) interconnect landing on multilayered metal contacts, and semiconductor structures formed therefrom

A contact element structure of a semiconductor device includes an opening positioned in an insulating material layer, the insulating material layer being positioned above a semiconductor substrate, and the opening having an upper sidewall portion, a lower sidewall portion, and a bottom surface portion. An insulating liner portion is positioned within the opening, the insulating liner portion covering the insulating material layer at the upper sidewall portion but not covering the insulating material layer at the lower sidewall portion. A contact liner is positioned within the opening and covers the insulating liner portion, the insulating material layer at the lower sidewall portion, and the insulating material layer at the bottom surface portion, and a conductive material is positioned in the opening and covers the contact liner.

Contact element structure of a semiconductor device

The present disclosure generally relates to semiconductor structures and, more particularly, to interconnect structures and methods of manufacture. The structure includes a metallization feature comprising a fill material and formed within a dielectric layer; at least one cap covering the fill material of the metallization feature, the at least one cap is comprised of a material different than the fill material of the metallization feature; and an interconnect structure in electrical contact with the metallization feature.

Interconnect structures

The present disclosure provides a contact element of a semiconductor device structure, wherein an opening is formed in an insulating material layer, the insulating material layer being provided over a semiconductor substrate. Within a lower portion of the opening, a contact liner portion is formed, the contact liner portion covering a bottom of the opening and partially covering a lower sidewall portion of the lower portion of the opening such that an upper sidewall portion at an upper portion of the opening is exposed to further processing. An insulating liner portion is formed within the opening, the insulating liner portion covering the exposed upper sidewall portion. Furthermore, a contact liner is formed within the opening, the contact liner covering the contact liner portion in the insulating liner portion, and the opening is filled with a conductive material.

Method of forming a contact element of a semiconductor device and contact element structure

Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.

Fabrication of IC structure with metal plug

The present disclosure relates to semiconductor structures and, more particularly, to seamless metallization structures and methods of manufacture. A structure includes: a contact opening formed in an oxide material and in alignment with an underlying structure; a metal liner lining the sidewalls and bottom of the contact opening, in direct electrical contact with the underlying structure; a conductive liner on the metal liner, within the contact opening; and tungsten fill material on the conductive liner and within the contact opening.

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Poughkeepsie, NY, United States of America

Jim Shih-Chun Liang