Altera Corporation

Jim Park

Bruce B Pedersen

Sergey Yuryevich Shumarayev

Rakesh H Patel

Wei-Jen Huang

Tony K Ngai

James G Schleicher

Victor Maruri

Peter J Kazarian

David Wolk Mendel

Michael David Hutton

Andrew Leaver

Bruce B Pederson

Stephanie T Tran

Guu Lin

Jay Schleicher

Brad Vest

David Karchmer

Mihail Iotov

Michael V Wenzler

Erhard Joachim Pistorius

A method for managing records in an object-oriented database is disclosed. Modified representations of data in fields of records is generated in response to patterns in the data. The modified representations of the data is compressed utilizing similarities in the modified representations of the data.

Method and apparatus for utilizing patterns in data to reduce file size

A method or apparatus that allows new devices to be easily integrated with computer aided design (CAD) tools via an easily extensible application programming interface (API). In an embodiment, new devices are added by reading a new device type and assigning a sequential index value. Index values are assigned to the new devices by appending a new device type to the end of an enumeration construct. When the data structure is compiled, the new device type is converted to a sequential index value. Data values for the new device are added to a data structure and can be accessed via the index value. Because the added device type is appended to the end of the enumeration construct, the index values assigned to the original data types remain unchanged. Consequently, recompilation is only required for applications that need to access the new devices and is unnecessary for the applications that do not use the new devices.

Method for adding device information by extending an application programming interface

Compiled configuration files for different programmable logic devices that are intended to be functionally equivalent may be compared using multiple different comparisons to assure functional equivalence. The different comparisons include a fitter or resource report comparison, an engineering bit settings report that compares vectors of bits that represent the settings of hard logic blocks, and comparisons based on location, connectivity and functionality. These comparisons are particularly well-suited for determining equivalence between different models of programmable logic devices, or even different types of devices such as field-programmable gate arrays as compared to mask-programmable logic devices.

Method and apparatus for comparing programmable logic device configurations

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Interconnection and input/output resources for programmable logic integrated circuit devices

Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.

Flexible macrocell interconnect

A graphical tool assists a user in migrating programming changes from one programmable logic device to another. The tool preferably compares a new user configuration dataset (e.g., the user configuration dataset including old features as well as newly-added features) for the 'origin' programmable logic device to the existing user configuration dataset (i.e., the user configuration dataset including only old features) for a 'destination' programmable logic device, and displays differences to the user. The tool preferably also assists the user to synchronize the devices by &#x201c;copying&#x201d; the new features of the user configuration dataset for one device into the old user configuration dataset for another device to the extent possible, by providing graphical inputs to allow the user to indicate which features should be synchronized, or to graphically manipulate the feature assignments directly.

Method and apparatus for comparing and synchronizing programmable logic device user configuration dataset versions

A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Interconnection resources for programmable logic integrated circuit devices

Growing community of inventors

San Jose, CA, United States of America

Jim Park