Tela Innovations, Inc.

Arm Physical Ip, Inc.

Jim Mali

Scott T Becker

Carole Lambert

Stephen Kornachuk

Michael C Smayling

Dhrumil Gandhi

Jonathan R Quandt

Daryl Fox

Betina Hold

A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a third gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a fourth gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

Cross-coupled transistor circuit defined on four gate electrode tracks

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

Cross-coupled transistor circuit defined on three gate electrode tracks

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a second gate electrode track. A second PMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along the first gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

Cross-coupled transistor circuit defined on two gate electrode tracks

A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

Enforcement of semiconductor structure regularity for localized transistors and interconnect

At least nine linear-shaped conductive structures (LCS's) are positioned in accordance with a first pitch. Five of the at least nine LCS's collectively form three transistors of a first transistor type and three transistors of a second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. Two transistors of the first transistor type and two transistors of the second transistor type are cross-coupled transistors. Each of four LCS's corresponding to the cross-coupled transistors has a respective electrical connection area located within the inner region. The two LCS's corresponding to the two transistors of the first transistor type of the cross-coupled transistors have electrical connections areas that are not aligned with each other. The four LCS's corresponding to the cross-coupled transistors include at least two different inner extension distances beyond their respective electrical connection areas.

Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods

A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes respective gate contacts and one or more conductive interconnect structures.

Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods

A first linear-shaped conductive structure (LCS) forms a gate electrode (GE) of a first transistor of a first transistor type. A second LCS forms a GE of a first transistor of a second transistor type. A third LCS forms a GE of a fourth transistor of the first transistor type. A fourth LCS forms a GE of a fourth transistor of the second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. Each of the first, second, third, and fourth LCS's has a respective electrical connection area. At least two of the electrical connection areas of the first, second, third, and fourth LCS's are located within the inner region. The first and fourth transistors of the first transistor type and the first and fourth transistors of the second transistor type form part of a cross-coupled transistor configuration.

Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods

A semiconductor device includes conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications

A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.

Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer

A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.

Circuits with linear finfet structures

A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature

Growing community of inventors

Morgan Hill, CA, United States of America

Jim Mali