Flir Systems, Incorporated

Jim Goodland

Theodore R Hoelter

Pierre M Boulanger

Barbara Sharp

Nicholas Högasten

Katrin Strandemar

Eric A Kurth

Marcel Tremblay

Mark Nussmeier

Brian B Simolon

Farhad Mirbod

Naseem Y Aziz

Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select a current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.

Abnormal clock rate detection in imaging sensor arrays

An infrared camera architecture includes, for an embodiment, an infrared detector, a substrate, a plurality of electrical components coupled to the substrate, and a pedestal made of a thermally conductive material and having a leg coupled to the substrate. The infrared detector is supported by and thermally coupled to the pedestal, with the pedestal thermally isolating the infrared detector from the plurality of electrical components.

Infrared camera architecture systems and methods

Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select the current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.

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Santa Barbara, CA, United States of America

Jim Goodland