Emulex Design & Manufacturing Corporation

Emulex Corporation

Praesidium, Inc.

Jim Donald Butler

David James Duckman

Raul Bersamin Oteyza

Daming Jin

Eddie Miller

Gian Franco Sacco

Joe Chung-Ping Tien

Richard Curtis Nordgran

Paolo Focardi

Weston Brent Johnson

Seth Campbell

Khanh Hue Huynh

Sujith Arramreddy

John Sui-kei Tang

Michael Scully Jordan

A occupant detection and monitoring system has a sensor unit having a radio wave transmitter, a radio wave receiver, and a wireless transmitter configured to detect and receive vital signs of an occupant; a user interface having a microcontroller, a wireless receiver configured to receive the wireless signals transmitted from the sensor unit, a means for user input, and a network card; and a means for alerting occupants and third-parties to a triggering event; wherein the microcontroller, based upon logic, activates the alerting means at the triggering event. The sensor unit may be a camera that detects the presence of an individual and register their unique heart rhythm for identification purposes. This camera can be installed at the entry points of a home, behind the counter of a business near a cash register or at a bank or any other place that desires to use surveillance as a form of security. The sensor unit may be a light bulb that comprises the components of the sensor unit. The sensor unit may be a contactless vital sign monitor capable of remotely monitoring one or more vital signs.

Home occupant detection and monitoring system

A home occupant detection and monitoring system has a sensor unit having a radio wave transmitter, a radio wave receiver, and a wireless transmitter configured to detect and receive vital signs of an occupant; a user interface having a microcontroller, a wireless receiver configured to receive the wireless signals transmitted from the sensor unit, a means for user input, and a network card; and a means for alerting occupants and third-parties to a triggering event; wherein the microcontroller, based upon logic, activates the alerting means at the triggering event.

In one embodiment of the invention, a method for protecting a content addressable memory is disclosed. The method includes storing a marker bit associated with each data block stored in a random access memory (RAM), states of the marker bit representing whether the data block was recently read from the RAM or recently written into the RAM; receiving a client address pointing to a starting address of a data block stored in the RAM; comparing the client address against one or more addresses stored in a content addressable memory (CAM) to determine a hit indicating the client address was stored in the CAM or a miss indicating the client address was not stored in the CAM; and in response to a miss, the method further includes checking a state of the marker bit associated with the data block pointed to by the client address.

Soft error protection for content addressable memory

A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network.

Autonomous mapping of protected data streams to fibre channel frames

A method and apparatus is disclosed for improving the MSI and MSI-X specifications by implementing an efficient delivery and clearing mechanism for interrupt conditions to increase performance between the driver and hardware/firmware interface while ensuring that no interrupts are lost in the process. In particular, an auto clear function is employed to eliminate the need for drivers in the host to send writes over the PCI-based bus to deassert and assert attention enable register bits and clear down attention register bits, and a fail safe mechanism is utilized to prevent lost interrupts.

Message signaled interrupt extended (MSI-X) auto clear and failsafe lock

A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.

Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes

A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a preferred embodiment, new host registers are implemented within controller circuitry of the peripheral device, the host registers being configured to be recognized by host software executed by host. The host device reads and writes to the host registers, which causes appropriate controller hardware to access the peripheral nonvolatile memory accordingly. By creating and implementing the new host registers, an enhanced controller is created that allows a host device to directly access peripheral memory, without peripheral processor assistance.

System and method for direct memory access from host without processor intervention wherein automatic access to memory during host start up does not occur

A method and system for allowing flexible control of access to a shared memory by multiple requesters. In a preferred embodiment, the invention arbitrates access to flash memory on a HBA between multiple host channels and HBA microprocessors, and eliminates contention possibilities for the flash during write cycles by the allowing a grant to be locked for a period defined by the flash write protocol and timing.

Multi-channel memory access arbitration method and system

Systems and techniques to track deferred data transfers on a system-interconnect bus. A deferral response initiates storage of information corresponding to the response and tracking of progress for a requested data transfer. A master device, such as a bus adapter, may include a split-transaction repository, timers, and a split-transaction monitor. The master device may include both hardware and firmware components, and may be designed to handle split responses as defined by a Peripheral Component Interconnect Extended standard.

Growing community of inventors

Costa Mesa, CA, United States of America

Jim Donald Butler