Taiwan Semiconductor Manufacturing Comp. Ltd.

Jim Cy Huang

Yu-Lien Huang

Hun-Jan Tao

Ling-Yen Yeh

Weng Chang

Kuang-Yuan Hsu

Fang Wen Tsai

Shun Wu Lin

Yi-Chen Huang

Li-Shiun Chen

A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.

Method for metal gate N/P patterning

Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.

Triangular space element for semiconductor device

A method for improving uniformity of stressors of MOS devices is provided. The method includes forming a gate dielectric over a semiconductor substrate, forming a gate electrode on the gate dielectric, forming a spacer on respective sidewalls of the gate electrode and the gate dielectric, forming a recess in the semiconductor adjacent the spacer, and depositing SiGe in the recess to form a SiGe stressor. The method further includes etching the SiGe stressor to improve the uniformity of SiGe stressors.

Resolving pattern-loading issues of SiGe stressor

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Baoshan, China

Jim Cy Huang