Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Jim Childers

Hiroshi Miyaguchi

Peter Reinecke

Moo-Taek Chung

Yutaka Takahashi

Herbert Meier

Andreas Hagl

Pravin P Patel

Klaus Seiberts

Manfred Becker

James D Gallia

Kevin Patrick Lavery

Seiichi Yamamoto

Mohammed Arefeen

An electronic device and method for half duplex data transmission in a long range keyless entry and go system, and more specifically to an RFID transponder, a corresponding read/write (R/W) unit and methods for operating the RFID transponder and the R/W-unit. There is a first coil, a second coil and a third coil, being arranged as a three-dimensional antenna, a first capacitor, a second capacitor and a third capacitor couplable in parallel to the first coil, the second coil and the third coil, respectively, for selectively forming a first, a second and a third parallel-resonant circuit for receiving radio signals, a series-resonant circuit for transmitting radio signals and a control stage configured to either use one of the first, second or third parallel-resonant circuits for receiving radio signals or the series-resonant circuit for transmitting signals.

Electronic device, method and system for half duplex data transmission

A keyfob is disclosed for use in detecting an attack on a vehicle. The keyfob includes a microcontroller, a wake receiver and an accelerometer. The wake receiver is configured to measure received signal strength and save the measured value in received signal strength indicator (RSSI). The accelerometer is used to generate acceleration data. The microcontroller detects an attack based on the RSSI and the acceleration data.

Relay attack prevention for passive entry/passive start systems

Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device (the driving through a transistor with a first drain-to-source impedance during the driving), and maintaining the Boolean state applied to the signal pad through the transistor with a second drain-to-source impedance, higher than the first drain-to-source impedance.

Method and system to reduce electromagnetic radiation from semiconductor devices

A method and apparatus independently controls the increasing rate and the decreasing rate a P-channel power FET and an N-channel power FET driving an inductive load. Circuits inhibit turning ON the P-channel FET until the voltage on the gate of the N-channel FET falls below its turn-on voltage threshold, and turning ON the N-channel FET until the voltage on the gate of the P-channel FET falls below its turn-on voltage threshold.

Method of controlling slope and dead time in an integrated output buffer with inductive load

This invention detects a stall in a stepper motor by determining a motor winding current for each stepper pulse and determining if the winding current of a particular stepper pulse meets predetermined criteria. The motor winding current may be determined by measuring a voltage across an ON field effect transistor during a stepper pulse and calculating a winding current using an assumed ON field effect transistor resistance. The predetermined criteria may by a calculated motor winding current greater than a predetermined threshold, greater than prior pulse by more than a predetermined threshold or greater than a prior pulse by more than a predetermined factor.

Method of stall detection for stepper motor system

A method and motor controller for sensing motor winding current. An FET drive transistor has its ON resistance periodically increased to about five times the normal ON resistance for short sensing intervals during motor drive. An analog-to-digital converting senses the voltage across this FET during the sensing intervals. The resulting digital signal is used to calculate motor current. The time at high ON resistance is much less than the time at normal. The ON resistance can be changed using two FETs or one FET with gate fingers over differing parts of the channel region.

Method of sensing motor winding current in integrated stepper motor buffer

A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.

Timing and control circuit and method for a synchronous vector processor

An electronic circuit has reduced controller memory requirements for multiple sequential instructions. The electronic circuit includes: a controller memory (1258) with addressable storage locations; a program counter (1548); control logic (1586) for receiving control information from an addressable storage location of the controller memory for performing logical operations on the control information and generating a control signal (1609) responsive to the control information; a repeat counter (1294) for receiving a repeat instruction signal from the controller memory (1258) and for sending a hold count signal (1233) to the program counter (1584) and the control logic (1586) such that the program counter (1584) continues to select the same addressable storage location and the control logic (586) repeats sending the control signal (1609); and a register address counter (1290) for receiving the control signal from the control logic (1586), the hold count signal (1233) from the repeat counter (1294) and a register address signal (1604) from the controller memory. The register address signal stored in the register address counter (1290) points to one of a plurality of registers. The register address counter (1290) receives and stores the address signal if the repeat counter (1294) fail to send the hold count signal and increments the register address signal to point to a next consecutive register if the repeat counter (1294) sends the hold count signal.

Electronic circuit for reducing controller memory requirements

Circuitry and method for performing a double instruction during a single clock cycle in a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The circuitry includes four sense amps per processor element and one ALU to enable reading of four data bits per clock cycle. The method includes reading data from each register file in a processor element and writing the data in one of the register file memory banks; enabling a 2:1 reduction in the amount of required instructions and a substantial reduction in overall cycle time.

Circuitry and method for performing two operating instructions during a

A power drain and noise reduction control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This control circuit substantially reduces the power drain by only powering up the portion of the circuit being written. Also noise which would otherwise be present on the data lines is reduced.

Data transfer control circuit with a sequencer circuit and control

A constant generator is described which provides a sequence of digital constants in a synchronous vector processor. The constant generator includes a constant loop memory for storing data words organized into a plurality of data constant patterns and an end of loop bit, a constant loop counter for supplying sequential addresses to the constant loop memory, and a constant loop counter controller for loading the counter with one of a set of predetermined starting addresses associated with a desired constant pattern stored in the constant loop memory. Additionally, a method of supplying a sequence of digital constants in said constant generator is disclosed and includes the steps of storing a plurality of data words in a plurality of constant patterns, where each constant pattern includes an end of loop bit, supplying an address to the constant loop memory and supplying sequential addresses to the constant loop memory.

Sequential constant generator system for indicating the last data word

A data processing apparatus includes a dual port data input register, first and second sequential ring counters, first and second register files, first and second data transfer circuits, a dual port data output register and N single bit processing elements. The dual port data input register has an M bit wide input port and an N bit wide output port. The first sequential ring counter cyclically selects one column of the data input register for input. The first data transfer circuit has a plurality of input segments, which are subsets of consecutive columns of the data input register. The first data transfer circuit transfers data from a selected row of the data input register to a selected row of the first register file for all columns of each input segment in a repetitive sequence of consecutive input segments in synchronism with said first sequential ring counter. The dual port data output register, the second register file, the second sequential ring counter and the second data transfer circuit are similarly organized to output data. Each of the N single bit processing elements is connected to a predetermined column of the first and second register files and capable of data processing operations under program control including data transfer to and from selected rows of said predetermined column of said first and second register files.

Growing community of inventors

Fort Bend, TX, United States of America

Jim Childers