Texas Instruments Corporation

Jim C Tso

Vipul C Patel

Kenneth A Poteet

David R Brown

A DRAM furnishes power management circuits that remove power from circuits on the DRAM that are not necessary for self-refresh and that turn on and off other circuits necessary for self-refresh in timed relation to the refresh cycle. The power management circuits include a counter and simple decoder circuits that decode the binary output of the counter.

DRAM power management with self-refresh

A 1M.times.2 parity DRAM is salvaged from a defective 1M.times.4 parity DRAM having two or less unrepairable memory quadrants. Circuits are designed so 'any' combination of 2 good quadrants can be accessed as a result of fuse blowing and steering logic which is controlled by the fuse signals.

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Sugarland, TX, United States of America

Jim C Tso