International Business Machines Corporation

Globalfoundries Inc.

Globalfoundrles Inc.

Jilei Yin

Kai Yang

Yang Fan Liu

Zhao Qing Zheng

Yang Liu

Adrian Stephen Butter

Bin Sun

Wei Jiang

Yijian Qi

A system and apparatus for obtaining clock synchronization of networked devices and related method are provided. Embodiments include a computer-implemented system, including a primary device having a first high accuracy timestamping assist (HATA) unit attached to a first physical layer; a first time stamping unit; a first clock control; a first medium access control layer connected to the first time stamping unit and the first physical layer via a medium independent interface. A secondary device includes a second HATA unit attached to a second physical layer; a second timestamping unit; a second clock control. The first and second HATA units are configured to detect a departure time, an arrival time, or a combination thereof of a first alignment marker over transmitter serializer and receiver deserializer interfaces of a data transmission between the primary device and the secondary device.

Nanosecond accuracy of timestamping by leveraging alignment marker and method for producing the same

Efficient codeword synchronization methods and systems for fiber channel protocol are disclosed. The method includes identifying a codeword boundary by detecting 100-bit known patterns in a bit codeword in a transmission.

Codeword synchronization for fiber channel protocol

Logic circuit for codeword synchronization for fiber channel protocol

Disclosed are Ethernet physical layer devices (e.g., a transceiver, a receiver and a transmitter) with integrated physical coding and forward error correction sub-layers. Each physical layer device includes a physical coding sub-layer (PCS), a forward error correction sub-layer (FEC) and integration block(s). Each integration block halts, for some number of clock cycles, a data stream in portions of a data path (e.g., portions of a transmitter (TX) data path or portions a receiver (RX) data path) within the PCS and the FEC in order to compensate for processing of that data stream by a data processor (e.g., a code word mark (CWM) inserter or a CWM remover) contained in the portion of the data path within the FEC. Use of such integration block(s) eliminates the need for redundant components in the PCS and FEC, thereby reducing latency, costs and chip area consumption. Also disclosed are associated methods.

Ethernet physical layer device having integrated physical coding and forward error correction sub-layers

Growing community of inventors

Beijing, China

Jilei Yin