Cadence Design Systems, Inc.

Jijun Chen

Igor Keller

Joel Reuben Phillips

Eddy Pramono

Pradeep Yadav

Nikolay Rubanov

Dhananjay Kumar Griyage

Joel R Philips

Accurate timing analysis during STA is performed using detailed waveform information in addition to the traditional slew information. A waveform memory system efficiently stores the detailed waveforms that are used in, calculated during, and propagated throughout timing analysis for a circuit design. During the STA process, for multiple modeled stages of circuit design, a waveform including information detailing the form of the waveform is compressed, stored in, decompressed, and retrieved from a memory system. The memory system provides for storage efficiencies including long-term and short-term storage areas, multi-level storage, and separate storage for each view evaluated during the STA.

Using waveform propagation for accurate delay calculation

A system and method for performing multi-mode multi-corner (MMMC) analysis such that multiple views or conditions can be analyzed together to improve runtime by taking advantage of common steps of analysis in different corners. Views are clustered based on their similarity to one another to take advantage of calculations and other tasks that may be shared between views during timing analysis. Then, during timing analysis, each net in the design is analyzed for each view.

View data sharing for efficient multi-mode multi-corner timing analysis

A lumped aggressor model is used to simulate multiple aggressor nets acting on a victim net. By lumping the aggressor nets together into a single input port, a single voltage excitation may be applied to the input port to simulate the model during static timing analysis. However, a record of each individual aggressor net and several associated attributes for each aggressor net is maintained such that the individual lumped aggressor nets may still be modeled as separate contributions to the attack on the victim net.

Lumped aggressor model for signal integrity timing analysis

In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (q) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (I) for input waveforms from the timing library; determining timing values (d) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (q) by minimizing a residual of a delay equation.

Growing community of inventors

San Jose, CA, United States of America

Jijun Chen