Via Technologies, Inc.

Shanghai Zhaoxin Semiconductor Co., Ltd.

Via Alliance Semiconductor Co., Ltd.

Jiin Lai

Weilin Wang

Jinkuan Tang

Chau-Chad Tsai

Buheng Xu

Jing Chen

Hui Jiang

Xiaoyang Li

Sheng-Chang Peng

Chi-Che Tsai

Chia-Hsin Chen

Zhenhua Huang

Kuo-Ping Liu

Hsin-Chieh Lin

Ruei-Ling Lin

Di Dai

Juanli Song

Zhi-Qiang Hui

Nai-Shung Chang

You-Ming Chiu

Chen-Ping Yang

Wayne Tseng

Peng Shen

Zhongmin Chen

Sheng-Chung Wu

Chun-Yuan Su

Chih-Kuo Kao

Xiaoliang Kang

Shanna Pang

Chad Tsai

Hung-Yi Kuo

Jiangli Zhu

Zhiqiang Hui

Heng-Chen Ho

Chin-Sung Hsu

Tse-Hsien Wang

Jyhfong Lin

Shuang-Shuang Qin

Chung-Che Wu

Terrance Shih

Bi-Yun Yeh

Wei-Long Chen

Xianpei Zheng

Xiu-Li Guo

Andrew Su

Jian Li

Ying Yu Tai

Yi-Lin Lai

Lei Huang

Chin-Yin Tsai

Mengchen Yang

Bo Zhao

Yang Shi

Ming-Shi Liou

Wei-Yu Wang

Jyh-Fong Lin

Ching-Fu Chuang

Yu-Wei Lin

Hao-Hsuan Chiu

Bowei Hsieh

Hsiang-I Huang

Hsuan-Yi Wang

Jenny Chen

Hsiang-Chou Huang

Victor Wu

Hung Yi Kuo

Wen-Hao Chuang

Peter Chia

Meng-Chen Yang

Fang-Yi Chen

Min-Hung Chen

Ling-Yan Zhong

Biyun Yeh

Ju Zhang

Andrew Chuang

Shan-Na Pang

Jin-Kuan Tang

Zhun Huang

Jih-Hsin Tsai

Meng-Cheng Ku

Huei-Li Chou

Xingchen Chen

Ying-Yu Tai

Win Sheng-Cheng

Edward Su

Wei-Lin Wang

Ziyang Li

A computing apparatus includes at least one general purpose processor, at least one coprocessor, and at least one application specific processor. The at least one general purpose processor is arranged to run an application, wherein data processing of at least a portion of a data processing task is offloaded from the application running on the at least one general purpose processor. The at least one coprocessor is arranged to deal with a control flow of the data processing without intervention of the application running on the at least one general purpose processor. The at least one application specific processor is arranged to deal with a data flow of the data processing without intervention of the application running on the at least one general purpose processor.

Computing apparatus and data processing method for offloading data processing of data processing task from at least one general purpose processor

A computing apparatus includes a first processing circuit and a second processing circuit. The first processing circuit includes a programmable logic circuit. The second processing circuit includes a general purpose processor that is used to execute an application program to download a bitstream to the first processing circuit for programming the programmable logic circuit to implement a direct memory access (DMA) engine and at least one physical engine (PE). The DMA engine is used to access a first memory through a DMA manner. The at least one PE is used to read data to be processed from the first memory through the DMA engine. The first processing circuit and the second processing circuit are disposed in one chip.

Computing apparatus utilizing programmable logic circuit to implement direct memory access engine and at least one physical engine and providing data to be processed to at least one physical engine through direct memory access engine

A bridge circuit includes an NVMe device controller, a network subsystem, and a data transfer circuit. The NVMe device controller is arranged to communicate with a host via a PCIe bus. The network subsystem is arranged to communicate with an NVMe-TCP device via a network. The data transfer circuit is coupled between the NVMe device controller and the network subsystem, and is arranged to deal with data transfer associated with the NVMe-TCP device without intervention of the host.

Bridge circuit for providing conversion between PCIe-NVMe protocol and NVMe-TCP protocol and computer system using the same

A multi-chip system and a cache processing method are provided. The multi-chip system includes multiple chips. Each chip includes multiple clusters, a crossbar interface, and a snoop system. Each cluster corresponds to a local cache. The crossbar interface is coupled to the clusters and a crossbar interface of another chip. The snoop system is coupled to the crossbar interface and performs unidirectional transmission with the crossbar interface. The snoop system includes a snoop table module and multiple trackers. The snoop table module includes a shared cache, which records a snoop table. Multiple trackers are coupled to the snoop table module, query the snoop table in the shared cache according to a memory access request initiated by one of clusters, and update the snoop table according to a query result. The snoop table corresponds to a storage structure of the local cache corresponding to the clusters in all chips.

Multi-chip system and cache processing method

The disclosure provides a data prefetching auxiliary circuit, a data prefetching method, and a microprocessor. The data prefetching auxiliary circuit includes a stride calculating circuit, a comparing module, a stride selecting module, and a prefetching output module. The stride calculating circuit receives an access address to calculate and provide a stride. The comparing module receives the access address and the stride, generates a reference address based on a first multiple, the access address and the stride, determines whether the reference address matches any of a plurality of history access addresses, and generates and outputs a hit indicating bit value. The stride selecting module receives the hit indicating bit value, and determines whether to output the hit indicating bit value based on a prefetch enabling bit value. The prefetching output module determines a prefetch address according to the output of the stride selecting module.

Data prefetching auxiliary circuit, data prefetching method, and microprocessor

The present disclosure provides a cache system and an operating method thereof. The system includes an upper-level cache unit and a last level cache (LLC). The LLC includes a directory, a plurality of counters, and a register. The directory includes a status indicator recording a utilization status of the upper-level cache unit to the LLC. The counters are used to increase or decrease a counting value according to a variation of the status indicator, record an access number from the upper-level cache unit, and record a hit number of the upper-level cache unit accessing the LLC. According to the counting value, the access number, and the hit number, the first parameters of the register are controlled, so as to adjust a utilization strategy to the LLC.

Cache system and operating method thereof

A microprocessor for neural network computing having a mapping table, a microcode memory, and a microcode decoding finite-state machine (FSM) is disclosed. According to the mapping table, a macroinstruction is mapped to an address on the microcode memory. The microcode decoding FSM decodes contents which are retrieved from the microcode memory according to the address, to get microinstructions involving at least one microinstruction loop that is repeated to operate a datapath to complete the macroinstruction.

Microprocessor for neural network computing and processing method of macroinstruction

A data accessing method of a switch for transmitting data packets between a first source node and a first target node and between a second source node and a second target node includes: transmitting a data packet to the switch via at least one of the first communication link and the third communication link and configuring the control unit to store information contained in the data packet into the storage unit; and retrieving the information contained in the data packet from the storage unit via at least one of the second communication link and the fourth communication link. The first source node, the second source node, the first target node and the second target node share the same storage blocks.

Switch and data accessing method thereof

A microprocessor provides at least two storage areas and uses a datapath for Booth multiplication. According to a first and second field of a microinstruction, the datapath gets multiplicand number supply data from the first storage area and multiplier number supply data from the second storage area. The datapath operates according to a word length indicated in a third field of the microinstruction. The datapath gets multi-bit acquisitions for Booth multiplication from the multiplier number supply data. The datapath divides the multiplicand number supply data into multiplicand numbers according to the word length, and performs Booth multiplication on the multiplicand numbers based on the multi-bit acquisitions to get partial products. According to the word length, the datapath selects a part of the partial products to be shifted and added for generation of a plurality of products.

Microprocessor with booth multiplication

A microprocessor with dynamically adjustable bit width is provided, which has a bit width register, a datapath, a statistical register, and a bit width adjuster. The bit width register stores at least one bit width. The datapath operates according to the bit width stored in the bit width register to acquire input operands from received data and process input operands. The statistical register collects calculation results of the datapath. The bit width adjuster adjusts the bit width stored in the bit width register based on the calculation results collected in the statistical register.

Microprocessor with dynamically adjustable bit width for processing data

A microprocessor with Booth multiplication, in which several acquisition registers are used. In a first word length, a first acquisition register stores an unsigned ending acquisition of a first multiplier number carried in multiplier number supply data, and a third acquisition register stores a starting acquisition of a second multiplier number carried in the multiplier number supply data. In a second word length that is longer than the first word length, a fourth acquisition register stores a middle acquisition of a third multiplier number carried in the multiplier number supply data. A partial product selection circuit is required for selection of a partial product, to get the partial product from Booth multiplication based on the third acquisition register (corresponding to the first word length) or based on the fourth acquisition register (corresponding to the second word length).

A microprocessor having the capability of executing a micro-instruction for series calculation is provided. The microprocessor includes an instruction decoder and an execution circuit for series calculation. The micro-instruction whose source operands correspond to an undetermined number x and a plurality of coefficients ato a(for xto x) is decoded by the instruction decoder. Based on x and ato a, the execution circuit for series calculation includes at least one multiplier for calculating exponentiation values of x (e.g. x), and includes at least one MAU (multiply-and-accumulate unit) for combining x, the exponentiation values of x, and the coefficients ato afor the series calculation.

Microprocessor with circuit for series calculation

A non-volatile memory (NVM) apparatus and an address classification method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller accesses the NVM in accordance with a write command of a host. The controller may perform the address classification method. The address classification method includes: providing a data look-up table, wherein the data look-up table includes a plurality of data entries, each of the data entries includes a logical address information, a counter value and a timer value; searching the data look-up table based on the logical address of the write command in order to obtain a corresponding counter value and a corresponding timer value; and determining whether the logical address of the write command is a hot data address based on the corresponding counter value and the corresponding timer value.

Non-volatile memory apparatus and address classification method thereof

A switch for transmitting data packets between at least one source node and at least one target node is provided. The switch includes a storage unit, a control unit, at least one receiving port and at least one transmitting port. The storage unit includes a plurality of storage blocks and configured to cache the data packets. The control unit is configured to manage the storage blocks. The switch receives and caches the data packets transmitted from the at least one source node via the receiving port and transmits the cached data packets to the at least one target node via the transmitting port. A data accessing method adapted for the switch is also provided.

A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ECC) circuit and a controller. The controller is coupled to the non-volatile memory and the ECC circuit. The controller may access a target wordline of the non-volatile memory in accordance with a physical address. The controller groups a plurality of wordlines of the non-volatile memory into a plurality of wordline groups, wherein different wordline groups have different codeword structures. The controller controls the ECC circuit according to the codeword structure of the wordline group of the target wordline, and the ECC circuit generates a codeword to be stored in the target wordline or check a codeword from the target wordline under control of the controller.

Controller device and operation method for non-volatile memory with 3-dimensional architecture

Growing community of inventors

Taipei, Taiwan

Jiin Lai