Samsung Electronics Co., Ltd.

Jihyun Choi

Jun Jin Kong

Junjin Kong

Haesuk Lee

Youngcheon Kwon

Jemin Ryu

Jaeyoun Youn

Hyunjoong Kim

Seunghyun Cho

Joonsik Sohn

Woongjae Song

Soowoong Ahn

Reum Oh

Eunae Lee

Won-hyung Song

Jinhyun Kim

Yesin Ryu

Beomyong Kil

Sunggi Ahn

Byungjin Kang

Yusun Cheong

Joosung Yun

Oh-Seong Kwon

Soonil Kwon

Byengseok Choi

DoHyung Lee

Gwanyoung Yoo

A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

Memory device for supporting new command input scheme and method of operating the same

A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.

Semiconductor memory device and system including the same

According to some example embodiments of the inventive concepts, there is provided a method of operating a stacked memory device including a plurality of memory dies stacked in a vertical direction, the method including receiving a command and an address from a memory controller, determining a stack ID indicating a subset of the plurality of memory dies by decoding the address, and accessing at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.

Stacked memory device and operating method thereof

A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.

Semiconductor memory devices and memory systems including the same

A test board includes a board substrate, a connector at a side of the board substrate, a plurality of device-under-test (DUT) boards which are connected to the board substrate and on which semiconductor devices are mounted as DUTs, and a plurality of DC-DC converters connected to the plurality of DUT boards. The plurality of DC-DC converters convert an input voltage supplied thereto via the connector into operating voltages, and provide the operating voltages to the semiconductor devices on the plurality of DUT boards corresponding thereto. The operating voltages are substantially the same.

Test board having semiconductor devices mounted as devices under test and test system including the test board

A semiconductor memory device includes a first memory area in the semiconductor memory device, and a second memory area in the semiconductor memory device. The second memory area is accessed independently of the first memory area based on a usage selecting signal. The first and second memory areas share command and address lines, and perform a rank interleaving operation based on the usage selecting signal.

Semiconductor memory device having rank interleaving operation in memory module

Growing community of inventors

Daegu, South Korea

Jihyun Choi