Samsung Electronics Co., Ltd.

Jihwan Hwang

Taehun Kim

Hyuekjae Lee

Jihwan Suh

Jiseok Hong

Soyoun Lee

Jihoon Kim

Unbyoung Kang

Tae Hong Min

Un-Byoung Kang

Sang-Sick Park

Ji-seok Hong

Geol Nam

Teakhoon Lee

Sang Cheon Park

Sangcheon Park

Sangsick Park

Jongpa Hong

Myungsung Kang

So Youn Lee

Jung-Hwan Kim

Kwang-Chul Choi

Yeongseok Kim

Young Kun Jee

Eunyeong Kim

A semiconductor package including a base chip; a semiconductor chip having a lower surface on which connection pads are disposed, the semiconductor chip being mounted on an upper surface of the base chip; a plurality of bumps on the connection pads and electrically connecting the base chip to the semiconductor chip; an adhesive film between the base chip and the semiconductor chip and fixing the semiconductor chip to the base chip; and an encapsulant on the base chip and encapsulating the semiconductor chip, wherein the semiconductor chip includes a central portion spaced apart from the upper surface of the base chip by a first distance, and an edge portion spaced apart from the upper surface of the base chip by a second distance, the edge portion being outside of the central portion, and a ratio of the second distance to the first distance is about 0.8 to about 1.0.

Semiconductor package

A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

Semiconductor package and a method for manufacturing the same

A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

Stacked semiconductor package

A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.

A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.

Semiconductor package including underfill material layer and method of forming the same

Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.

Semiconductor package having stacked semiconductor chips

A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 &#x3bc;m to 100 &#x3bc;m, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.

Semiconductor packages having improved reliability in bonds between connection conductors and pads and methods of manufacturing the same

According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

Die-to-wafer bonding structure and semiconductor package using the same

Semiconductor packages having improved reliability in bonds between connection conductors and pads

Growing community of inventors

Hwaseong-si, South Korea

Jihwan Hwang