Texas Instruments Corporation

Jihong Chen

Kaiping Liu

Zhiqiang (Jeff) Wu

Henry Litzmann Edwards

Amitabh Jain

Kenneth James Maggio

Jeffrey R Debord

Toan Tran

Michael C Smayling

John Anthony Rodriguez

Srinivasan Chakravarthi

Antonio Luis Pacheco Rotondaro

Eddie Hearl Breashears

Alister C Young

An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1&#xd7;10cmn-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1&#xd7;10cmp-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

Method of forming a CMOS-based thermoelectric device

CMOS-based thermoelectric device with reduced electrical resistance

The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.

Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor

The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.

Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same

A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

Reducing the migration of grain boundaries

The present invention provides a semiconductor devicehaving an angled compensation implant, a method of manufacture therefore and a method of manufacturing an integrated circuit including the angled compensation implant. In one embodiment, the method of manufacturing the semiconductor deviceincludes creating a halo implantin a substrate, introducing a compensation implantin the substrateat an angle abnormal to the substrateand forming a source/drain regionabove the compensation implant, the angle reducing a capacitance associated with the halo implantor the source/drain region. The method further includes placing a gate structureover the substrate

Semiconductor device having an angled compensation implant and method of manufacture therefor

A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.

Process method of source drain spacer engineering to improve transistor capacitance

A semiconductor device (10) of the present invention has a gate (32) insulatively disposed above the substrate, source and drain regions (36, 38) disposed near the surface in the substrate adjacent opposite sides of the gate (32), and a field oxide region (26) disposed in the surface of the substrate surrounding the source and drain regions (36, 38) and defining an active moat region (20). The channel stop region (24) is disposed below the field oxide region (26) and is spaced from the active moat region (20) with a predetermined spacing.

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Plano, TX, United States of America

Jihong Chen