Intel Corporation

Jiho Kang

James Jeong

Puneesh Puri

Kevin J Lee

Andrew W Yeoh

Hiten Kothari

John Muirhead

Adwait Telang

Nitin M Patel

Carole C Montarou

Ramanan Ehamparam

Ebubekir Dogan

Hsiao-Kang Chang

James Y Jeong

Integrated circuit (IC) structures include transistor devices with interconnect structures, e.g., a source contact, drain contact, and/or gate contact. The interconnect structures have rounded top surfaces. Contouring the top surfaces of transistor contacts may decrease the likelihood of electrical shorting and may permit a larger volume of insulating dielectric between adjacent contacts.

Integrated circuit structures with contoured interconnects

An embodiment includes a semiconductor structure comprising: a backend portion including a plurality of metal layers between bottom and top metal layers; the top metal layer including a top metal layer portion having first and second opposing sidewall surfaces and a top surface that couples the sidewall surfaces to one another; an insulator layer directly contacting the top surface; and a via coupling a contact bump to the top metal layer portion; wherein a first vertical axis, orthogonal to a substrate coupled to the backend portion, intercepts the contact bump, the nitride layer, the via, and the top metal layer portion. Other embodiments are described herein.

Anchored interconnect

Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an integrated circuit includes a silicon semiconductor substrate having one or more through-silicon vias (TSVs), although other through-body vias can be used as will be appreciated in light of this disclosure. Each TSV extends through at least a portion of the substrate, for example, from one side (e.g., top) of the substrate to the opposite side of the substrate (e.g., bottom), or from one internal layer of the substrate to another internal layer. A liner is disposed between the substrate and each TSV. The liner is formed of multiple alternating layers of dissimilar insulation films (e.g., tensile films and compressive films) sandwiched together.

Through-body via liner deposition

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a 'plate through resist' type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias

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Beaverton, OR, United States of America

Jiho Kang