Cirrus Logic Inc.

Jihad Y Abudayyeh

Stephen A Smith

Daniel G Bezzant

Narasimha R Nookala

Arunachalam Vaidyanathan

Ashutosh S Dikshit

Sanjiv D Pathak

Bryan Michael Richter

Dave M Singhal

Chester F Bassetti

Sriram Ramamurthy

Kasturiraman Gopalaswamy

Jafar Naji

Reza G Omid

A method and circuit to regulate a random waveform signal to ensure that the LED indicator driven by the waveform signal is visible to the human eye is provided. The method and circuit first determines whether there is a pulse occurring. If an on-going pulse is detected, the regulated waveform signal is driven HIGH for at least 8 clock cycles. If no on-going pulse is detected, the regulated waveform signal is driven LOW for at least 8 clock cycles.

Apparatus and method for shaping random waveforms

An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software that was written for previous hardware. Versions of software written for previous hardware attempt non-native register accesses for which the integrated circuit is designed to emulate the non-native register set. Versions of software specifically written for the present hardware attempt native register accesses for which no emulation is necessary. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode the interrupt information is written to an appropriate register and then mapped into the appropriate bits of the physical register set. In the second mode the interrupt information is written directly to the appropriate register. In both the first and second modes, steering bits from the appropriate register are used to map system, management and wakeup interrupts to the appropriate interrupt pad where the interrupt request signal is then shaped.

Method and apparatus for providing register and interrupt compatibility

An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software. Software may attempt non-native register accesses; the integrated circuit of the present invention will emulate a non-native register set. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode, the interrupt information is written to an appropriate register and then mapped into appropriate bits of the physical register set. In the second mode, interrupt information is written directly to the appropriate register.

Method and apparatus for providing register compatibility between

A peripheral device capable of generating interrupt request signals compliant with the Industry Standard Architecture (ISA) protocol, and the Peripheral Component Interconnect (PCI) protocol. The peripheral device comprises a signal generator block which selectively generates either the interrupt request signals of the PCI protocol or a set of bits representative of interrupt request signals of the ISA protocol. The set of bits are transferred serially to a converter circuit which generates the interrupt request signals of the ISA protocol based on the bits. The signal generator block generates bits in such a way as to support both pulse mode and level mode interrupt request signals for the ISA protocol.

Apparatus and method for supporting multiple interrupt protocols with

A method and apparatus for increasing the perceived gradation of the shades in visual displays is disclosed. A plurality of signals control the intensity of a sub-pixel of a display so that display can exhibit a native number of shades. Frame rate modulation techniques are used to increase the perceived gradation. Finally, flicker is reduced by spreading the phases of the modulating pixels across time, and the horizontal and vertical axes of the display.

Apparatus for shade gradation enhancement and flicker reduction in

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Fremont, CA, United States of America

Jihad Y Abudayyeh