International Business Machines Corporation

Jih-Kwon Peir

Joseph L Temple, Iii

Lishing Liu

Stephen E Bello

David R Pruett

Kien Anh Hua

Anderson H Hunt

Joseph O Celtruda

Kein A Hua

A multiprocessor computer system and associated method having processing error detection capability is disclosed for error-free processing of an instruction set. The instruction set is replicated and processed substantially in parallel through a plurality of processing nodes of the computer system. Each processing node collects a compressed hardware signature commensurate with and derived from the execution of the instruction set. Subsequent instruction set processing, the collected hardware signatures from each processing node are compared and the presence or absence of a processing error is determined with reference to a predetermined voting scheme. Processing of the instruction sets through the plurality of processing nodes is typically asynchronous with synchronization occurring subsequent each processor's execution of the instruction set, such that each processor can be driven by an independent clock.

Fault-tolerant multiple processor system with signature voting

This invention implements a cache access system that shortens the address generation machine cycle of a digital computer, while simultaneously avoiding the synonym problem of logical addressing. The invention is based on the concept of predicting what the real address used in the cache memory will be, independent of the generation of the logical address. The prediction involves recalling the last real address used to access the cache memory for a particular instruction, and then using that real address to access the cache memory. Incorrect guesses are corrected and kept to a minimum through monitoring the history of instructions and real addresses called for in the computer. This allows the cache memory to retrieve the information faster than waiting for the virtual address to be generated and then translating the virtual address into a real address. The address generation machine cycle is faster because the delays associated with the adder of the virtual address generation means and the translation buffer are bypassed.

Translation look ahead based cache access

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Fishkill, NY, United States of America

Jih-Kwon Peir