Taiwan Semiconductor Manufacturing Comp. Ltd.

Jih-Hwa Wang

Su-Yu Yeh

Chung-Te Lin

Pu-Fang Chen

Otto Chen

Chin-Te Huang

Fang-Chi Chien

Tung-Li Lee

Chie-Ming Yang

Jun-Yang Lai

Meng-Shiun Shieh

Jang-Cheng Hsieh

Chou-Jie Tsai

Chien-Jiun Wang

Yen-Yi Lin

A method for identifying a drifted dose integrator in an implantation system and an implantation system are provided. The implantation system includes a first dose integrator and a second dose integrator. The first dose integrator includes a first input configured to receive a first current generated from charges carried by implanted ions in a wafer, and a first output configured to output a first accumulated dosage value. The second dose integrator includes a second dose integrator including a second input configured to receive a second current generated from the charges carried by the implanted ions in the wafer, and a second output configured to output a second accumulated dosage value. The implantation system further includes a processing unit comparing the first accumulated dosage value and the second accumulated dosage value to detect a drift in one of the first and the second dose integrators.

Preventing dosage drift with duplicate dose integrators

A method for forming lining oxide in an opening for a shallow trench isolation and a method for forming a shallow trench isolation incorporating a lining oxide layer are described. In the method for forming lining oxide, a silicon substrate is first provided, followed by a process of forming a pad oxide layer and a silicon nitride mask sequentially on top of the silicon substrate. A trench opening is then patterned and formed in the silicon substrate for the shallow trench isolation. The silicon substrate is then annealed at a temperature of at least 1,000&deg; C. in a furnace in an environment that contains not more than 10 vol. % oxygen. A lining oxide layer is formed in the same furnace used for annealing the structure of the trench opening in the silicon substrate.

Method for forming lining oxide in shallow trench isolation incorporating pre-annealing step

A method for forming silicon oxide layers on silicon wafers by a wet oxidation process that utilizes a dual-stage pyrolysis is described. The process can be carried out by flowing a first H /O mixture that has a first H /O gas mixture ratio into a torch and then feeding water vapor generated into the wet oxidation chamber to form a first layer of silicon oxide, and then flowing a second H /O mixture that has a second H /O gas mixture ratio into the torch and feeding water vapor generated into the wet oxidation chamber for forming a second thickness of the silicon oxide layer. The second H /O ratio is smaller than the first H /O ratio by at least of the value of the first H /O ratio. For instance, when the first H /O ratio used is large than 1.5, the second H /O ratio used is less than 1.2. In one example, the first H /O gas mixture ratio utilized is 1.8, while the second H /O gas mixture ratio utilized is 1.0. It has been found that by reducing the hydrogen content, i.e. by decreasing the H /O gas mixture ratio, the partial pressure of the water vapor generated is reduced which minimizes the loading effect in the furnace tube during the wet oxidation process and improves the uniformity of the silicon oxide layers deposited.

Dual-stage wet oxidation process utilizing varying H2/O2 ratios

A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by thermal annealing is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. The semiconductor substrate is annealed by rapid thermal annealing (RTA). Thereafter, an oxide layer is deposited overlying the silicide layer. Because the silicide layer has been annealed, silicon atoms are prevented from diffusing into the silicide layer and forming voids in the polysilicon layer. The silicide, polysilicon and gate silicon oxide layers are patterned to complete fabrication of a gate electrode in the manufacture of an integrated circuit device.

Thermal annealing for preventing polycide void

Growing community of inventors

Hsin-Chu, Taiwan

Jih-Hwa Wang