Spansion Llc.

Jih Hong Beh

Ken Cheong Cheah

Mee-Choo Ong

Wei-Kent Ong

Sheau-Yang Ch'ng

Boon-Weng Teoh

Sie Wei Henry Lau

A memory operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory. In the normal mode of operation, the memory can perform the asynchronous read operation, the page read operation, an asynchronous write operation in which a word of electronic data is stored into the memory that correspond to the address, or a page write operation in which a page electronic data is stored into the memory that correspond to the multiple addresses.

For test (DFT) read speed through transition detector in built-in self-test (BIST) sort

A method of reading data in and outputting data from a memory structure includes a buffer. In the present method, first read operation is undertaken to read a first set of data in the memory structure and provide data of the first set of data to the buffer, using an output clock. A first output operation is undertaken providing data read in the first read operation from the buffer, and a second read operation is undertaken to read a second set of data in the memory structure and provide data of the second set of data to the buffer, using the output clock. A second output operation is undertaken providing data read in the second read operation from the buffer. In the event that the completion of the first output operation would occur prior to the completion of the provision of the data of the second set of data to the buffer, a flexible time delay approach is undertaken so that, between the completion of the first output operation and the beginning of the second output operation, the minimum number of latencies are added as needed to insure that the provision of the data of the second set of data to the buffer is completed prior to the initiation of the second output operation.

Flexible latency in flash memory

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Bukit Mertajam, Malaysia

Jih Hong Beh