Taiwan Semiconductor Manufacturing Comp. Ltd.

Jih-Churng Twu

Syun-Ming Jang Jang

Ying-Ho Chen

Tsu Shih

Chen-Hua Douglas Yu

Chia-Chun Cheng

Hom-Chung Lin

Feng-Yu Chen

Ming-Dar Guo

Shau-Lin Shue

Tsung-Chieh Tsai

Tien-Chen Hu

Rong-Hui Kao

Chin-Yun Chen

Yi-Ting Chang

Weng Chang

Wei-Ming You

Shu-Han Chao

Jian-Lun Lo

Yi-Chi Huang

Yu-Chien Hsiao

Yuan-Hsiao Su

Yueh-Ting Yang

Chi-Ying Chang

Anthony Yen

Ming-Hsing Tsai

Chih-Hang Tung

Kuo-Bin Huang

Su-Chun Yang

Chin-Hsiung Ho

Tsung-Min Lin

Yu-Chi Tsai

Jiung Wu

Ching-Shan Lu

Hung-Ta Huang

Chao-Po Lu

Juin-Jie Chang

Wen-Jye Tsai

Fu-Su Lee

Tai-Hsiang Lin

Ming Te More

Stanley Huang

Hsueh-Li Sun

Juinn-Jie Chang

Tom Tseng

Roung-Hui Kao

Ching Shan Lu

Sheng-Hsiung Tseng

Yao-Pin Huang

A die stacking structure, a semiconductor package and a method for forming the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; and a stack of dielectric layers, extending in between the second device dies, and laterally enclosing each of the second device dies. The dielectric layers are respectively formed of a spin-on-glass (SOG) or a polymer, and a lower one of the dielectric layers has a thickness greater than a thickness of another one of the dielectric layers at a higher level.

Die stacking structure, semiconductor package and formation method of the die stacking structure

A method includes transferring a tool monitoring device to a load port of a tool. An environmental parameter of the load port is monitored by the tool monitoring device. The tool monitoring device is removed from the load port after the environmental parameter of the load port is monitored. A door of the tool in front of the load port is closed. The door of the tool is kept closed during a period from a time of transferring the tool monitoring device to the load port to a time of removing the tool monitoring device from the load port.

Method of monitoring tool

An ion implantation system includes an ion implanter containing an ion source unit and a dopant source gas supply system. The system includes a dopant source gas storage tank inside a gas box container located remotely to the ion implanter and a dopant source gas supply pipe configured to supply a dopant source gas from the dopant source gas storage tank to the ion source unit. The dopant source gas supply pipe includes an inner pipe, an outer pipe enclosing the inner pipe, a first pipe adaptor coupled to first end of respective inner and outer pipes, and a second pipe adaptor coupled to seconds end of respective inner and outer pipes opposite the first end. The first pipe adaptor connects the inner pipe to the dopant source gas storage tank and the second pipe adaptor connects the inner pipe to the ion source unit.

Gas delivery system for ion implanter

In some embodiments, a system for monitoring a tool is provided. The system includes a tool monitoring device, a transporting system and an external apparatus. The tool monitoring device is configured to monitor an environmental parameter of a load port of a tool. The tool monitoring device includes a wafer pod and a monitoring module disposed in the wafer pod. The monitoring module includes at least one sensor, a computer coupled to the at least one sensor, a power supply electrically coupled to the at least one sensor and the computer, and a wireless unit coupled to the computer. The transporting system is configured to transfer the tool monitoring device from one load port to another load port. The external apparatus is coupled to the tool monitoring device.

Tool monitoring device and method of monitoring tool

A method for fault detection in a fabrication tool is provided. The method includes processing a semiconductor wafer in a fabrication tool according to a plurality of process events of a process run. The method further includes measuring humidity in the fabrication tool in at least one of the process events. The method also includes comparing the humidity measured in one of the process events with an expected humidity associated with the process event. In addition, the method includes based on the comparison, indicating an alarm condition when a difference between the measured humidity and the expected humidity exceeds a range of acceptable values associated with the process event.

Fault detection method in semiconductor fabrication facility

A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers in a furnace. The furnace includes a first end thermal zone, a middle thermal zone and a second end thermal zone arranged in sequence. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. The method also includes supplying a purging gas into the furnace after the formation of the thin film. In addition, the method includes controlling the temperature of the furnace in a second thermal mode during the supply of the purging gas. The temperature distributions of the furnace are different in the first and second thermal modes.

Method for controlling temperature of furnace in semiconductor fabrication process

A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. In the first thermal mode, a first end thermal zone, a middle thermal zone and a second end thermal zone of the furnace which are arranged in sequence have a gradually increasing temperature. The method also includes controlling the temperature of the furnace in a second thermal mode after the formation of the thin film. In the second thermal mode, the first end thermal zone, the middle thermal zone and the second end thermal zone of the furnace have a gradually decreasing temperature.

A method of monitoring and adjusting the position of a wafer with respect to an ion beam including setting the position of a wafer holder so that a wafer to be held therein is positioned at a tilt angle of 45 degrees and a twist angle of 45 degrees with respect to the path of an ion beam; positioning a n-type wafer without screen oxide in the wafer holder; implanting boron species into a region of the wafer at 160 KeV and a dose level of 5.0&#xd7;10atoms/cm; periodically measuring the sheet resistivity of a implanted wafer and readjusting the wafer tilt angle when the sheet resistivity is greater than 30 ohms/square.

Method of monitoring high tilt angle of medium current implant

A continuous and integrated cleaning/preparation process is described to condition a silicon surface for the formation of a high quality ultra thin gate oxide described. The process is conducted with the wafer surface immersed in an aqueous solution the composition of which is varied continuously according to the steps of the process. The process includes the initial removal of contaminants and particulates followed by the removal of a native oxide. Next the silicon surface is dressed in the present of both HF and ozone by removing a thin surface layer. Any interfacial contamination or surface structural defects which lay under the native oxide are thereby removed. Next a high quality chemical oxide is grown by the action of the ozone in the aqueous bath. The chemical oxide is found to be of higher purity and structural quality than native oxide and provides a superior passivation of the active surface prior to gate oxidation. The chemical oxide is incorporated into the final gate oxide and, because of it's high quality, results in improved device performance of the final gate oxide.

Method for forming a high quality chemical oxide on a freshly cleaned silicon surface as a native oxide replacement

A linear chemical mechanical polishing apparatus that is equipped with a programmable pneumatic support platen and a method for controlling the polishing profile on a wafer surface during a linear CMP process are disclosed. The programmable pneumatic support platen is positioned juxtaposed to a bottom surface of a continuous belt for the linear CMP apparatus and positioned corresponding to a position of the wafer carrier so as to force the polishing pad against the wafer surface to be polished. The support platen has a predetermined thickness, a plurality of apertures through the thickness and a plurality of openings in a top surface in fluid communication with a gas source through the plurality of apertures.

Linear chemical mechanical polishing apparatus equipped with programmable pneumatic support platen and method of using

A method including operating an ion implanted to implanting ions in a semiconductor wafer at a first ion dose level; performing a first thermal wave measurement to obtain the first thermal wave value; placing the semiconductor wafer in a rapid thermal annealing furnace and operating the furnace to rapidly heat the semiconductor wafer at a first rate for a first time period and so that the wafer is heated with intent of achieving a wafer temperature of 500&deg; C.; performing a second thermal wave measurement to obtain a second thermal wave value; comparing the difference between the first thermal wave value and the second thermal wave value to a target range of 376.5-382.5 and rejecting the wafer as being outside of an acceptable specification if the difference is outside of the target range.

Metrology for monitoring a rapid thermal annealing process

An improved and new process, used for the elimination of copper line damage, copper defects, non-uniformity improvement, with low dishing and erosion, in damacene processing, is disclosed. This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the elimination of copper line damage for damascene processing, by depositing a multilayer interface material, consisting of a mechanically hard film and a soft film, over a low dielectric constant, interlevel metal dielectric (IMD), and subsequently chemical mechanical polishing (CMP) back the excess material to planarize the surface.

Multilayer interface in copper CMP for low K dielectric

A ventilated platen/polishing pad assembly for chemical mechanical polishing copper conductors on a semiconductor wafer is disclosed. The ventilated platen is constructed by a platen having a multiplicity of apertures through a thickness of the platen, and a polishing pad that has a multiplicity of apertures for fluid communication with the multiplicity of apertures in the platen such that a gas can flow through the ventilated platen and the ventilated polishing pad to mix with a polishing slurry solution dispensed on top of the polishing pad. When an oxidizing gas is mixed with the slurry solution, the mass transfer process during the chemical mechanical polishing can be improved and thus improving the polishing uniformity of the copper surface. The invention further discloses a method for chemical mechanical polishing copper conductors on a semiconductor wafer by dispensing a polishing slurry/oxidizing gas mixture onto a top surface of a polishing pad for engaging a wafer surface and thus improving the polishing uniformity and preventing corrosion or erosion of the fresh copper surface by the acidic or basic components contained in the slurry solution.

Ventilated platen/polishing pad assembly for chemcial mechanical polishing and method of using

A method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas and wherein there is at least one low voltage area in which a low voltage transistor will be formed and at least one high voltage area in which a high voltage transistor will be formed. The surface of the semiconductor substrate is wet oxidized to form a first layer of gate oxide on the surface of the semiconductor substrate in the active areas. The low voltage active area is covered with a mask. The surface of the semiconductor substrate is wet oxidized again where it is not covered by the mask to form a second layer of gate oxide under the first gate oxide layer in the high voltage active area. The mask is removed. A layer of polysilicon is deposited overlying the first gate oxide layer in the low voltage active area and overlying the second gate oxide layer in the high voltage active area and patterned to form gate electrodes for the low voltage and high voltage transistors in the fabrication of an integrated circuit.

Formation of dual gate oxide by two-step wet oxidation

An electrostatic charge-free solvent-type dryer for drying semiconductor wafers after a wet bench process is disclosed in a preferred embodiment and in an alternate embodiment. In the preferred embodiment, the electrostatic charge-free solvent-type dryer is constructed by a tank body, a wafer carrier, an elevator means, a tank cover and a conduit for feeding the flow of solvent vapor. At least one of the tank cover, the conduit for feeding the flow of solvent vapor and the plurality of partition plates is fabricated of a non-electrostatic material such that electrostatic charge is not generated in the flow of solvent vapor. In the alternate embodiment, a deionizer is further provided in the tank cavity for producing a flux of positive ions to neutralize any negative ions that are possibly produced in the flow of solvent vapor.

Electrostatic charge-free solvent-type dryer for semiconductor wafers

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Chung-Ho, Taiwan

Jih-Churng Twu