Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Jih-Chao Chiu

Chee-Wee Liu

Wei-Jen Chen

Ya-Jui Tsou

Shao-Yu Lin

Hsin-Cheng Lin

Song-Ling Li

Tao Chou

A memory device includes a memory array, a first reference voltage circuit, a first read voltage control circuit and a first write voltage control circuit. The first reference voltage circuit is configured to provide a first reference voltage signal having a first voltage level to the memory array. The first read voltage control circuit is configured to adjust the first reference voltage signal to a second voltage level when the memory array is read. The first write voltage control circuit is configured to adjust the first reference voltage signal to a third voltage level when the memory array is written. The second voltage level is higher than the first voltage level, and the third voltage level is lower than the first voltage level.

Memory device adjusting reference voltage signal

A memory device includes a spin-orbit-transfer (SOT) bottom electrode, an SOT ferromagnetic free layer, a first tunnel barrier layer, a spin-transfer-torque (STT) ferromagnetic free layer, a second tunnel barrier layer and a reference layer. The SOT ferromagnetic free layer is over the SOT bottom electrode. The SOT ferromagnetic free layer has a magnetic orientation switchable by the SOT bottom electrode using a spin Hall effect or Rashba effect. The first tunnel barrier layer is over the SOT ferromagnetic free layer. The STT ferromagnetic free layer is over the first tunnel barrier layer and has a magnetic orientation switchable using an STT effect. The second tunnel barrier layer is over the STT ferromagnetic free layer. The second tunnel barrier layer has a thickness different from a thickness of the first tunnel barrier layer. The reference layer is over the second tunnel barrier layer and has a fixed magnetic orientation.

Memory device and formation method thereof

A method includes forming a fin over a substrate, the fin comprising alternately stacking first oxide-based semiconductor layers and second oxide-based semiconductor layers, removing the second oxide-based semiconductor layers to form a plurality of spaces each between corresponding ones of the first oxide-based semiconductor layers, and depositing in sequence a gate dielectric layer and a gate metal into the plurality of spaces each between corresponding ones of the second oxide-based semiconductor layers.

Semiconductor device with oxide-based semiconductor channel

Growing community of inventors

Taipei, Taiwan

Jih-Chao Chiu