International Business Machines Corporation

Ayla Networks, Inc.

Amazon Technologies, Inc.

Jigar Vora

John D Davis

Paul Alan Bunce

Diana M Henderson

Adrian Caceres

Joseph R Eykholt

Sudha Sundaresan

Daniel Myers

Marko Kiiskila

Vishwesh Pai

David Russell Friedman

Haoqing Geng

Pablo Sebastián Rivera

Yuen H Chan

Olusanya Temitope Soyannwo

Makarand Damle

Aditya Bhave

Yipei Wang

Ankit Premrajka

Systems and methods for functionality management of devices are disclosed. Multiple computing devices may be located in the same environment and/or space and at least two of those computing devices may be configured to perform a given functionality. In these and other examples, one of the devices may be identified as a primary device and the other devices may be identified as secondary devices based on, for example, historical usage data, audio-signal data, computer-vision analysis, and/or one or more other criteria. The functionality may be disabled on the secondary devices until the secondary devices are utilized and/or until a triggering event occurs.

Functionality management for devices

In an embodiment, a processing device receives an instruction to schedule an event associated with a remote target device, generates a schedule for the remote target device, and transmits the schedule to the remote target device. The processing device receives usage information from the remote target device and additional usage information from other remote devices. The processing device applies a machine learning algorithm to the usage information and the additional usage information to determine an update to the schedule. The processing device updates the schedule and sends the update to the remote target device.

Compact schedules for resource-constrained devices

A hardware module for an embedded system comprises a network adapter, a memory and a processing device. The memory stores a shared key and a key identifier (ID) associated with the shared key. The processing device is to connect to a local area network (LAN) using the network adapter. The processing device is further to receive a first notification from a computing device that is also connected to the LAN and determine whether the computing device has access to a copy of the shared key based on the key identifier (ID). Responsive to determining that the computing device has access to the copy of the shared key, the processing device is to use the shared key to generate a session key for a session with the computing device. The processing device may then encrypt communications to the computing device using the session key.

Communication module for embedded system

A gateway device includes a first interface to connect to an internet protocol (IP) network and a second interface having a first communication protocol to connect to one or more devices. The gateway device receives an instruction to initiate an attribute update for a device from a remote server via the first interface, the first instruction having a first format. The gateway device determines the attribute update and a virtual device identifier associated with the first device from the first instruction. The gateway device determines the first communication protocol and a first device based at least in part on the first virtual device identifier. The gateway device generates a command for the first device to perform the first attribute update, the command having a second format based at least in part on the first communication protocol, and sends the command to the first device via the second interface.

Management of multi-radio gateway device using virtual gateway device

A server determines a plurality of device templates that define a plurality of device attributes of a remote device connected to a gateway device. The server creates a virtual device from the plurality of device templates, wherein the virtual device is a virtual representation of the remote device. The server determines an attribute update for a first device attribute of the remote device. The server updates a second device attribute of the virtual device. The server generates an instruction for the gateway device to initiate the attribute update for the first device attribute. The server transmits the instruction to the gateway device, wherein the instruction causes the gateway device to generate a command for the remote device to perform the attribute update on the device attribute.

Management of gateway device using virtual gateway device

A processing device executing a scheduler receives, by a device, a schedule from a remote server computing device, the schedule having a compact format that is understood by the device. The device stores the schedule and the processing device parses the schedule to identify a scheduled event. The processing device executes the scheduled event at a specified time in accordance with the schedule even in the absence of a network connection between the device and the remote server computing device.

Proximity based communication with embedded system

Embodiments of the disclosure include a cache array having a plurality of cache sets grouped into a plurality of subsets. The cache array also includes a read line configured to receive a read signal for the cache array and a set selection line configured to receive a set selection signal. The set selection signal indicates that the read signal corresponds to one of the plurality subsets of the cache array. The read line and the set selection line are operatively coupled to the plurality of cache sets and based on the set selection signal the subset that corresponds to the set selection signal is switched.

Cache array with reduced power consumption

A computing device connects to a local area network (LAN) and determines whether a device comprising an embedded system is also connected to the LAN. Responsive to determining that the device is connected to the LAN, the computing device establishes a first session with the embedded system of the device over the LAN and then communicates with the embedded system of the device via the first session.

Embodiments include a high frequency write through memory device including a plurality of memory cells and a plurality of local evaluation circuits. Each of the plurality of local evaluation circuits are coupled to at least one of the plurality of memory cells and are configured to prevent data stored in the coupled memory cells from being written to a latch node during a write through operation.

High frequency write through memory device

A memory apparatus includes a plurality of memory arrays, each memory array including a plurality of memory cells. The apparatus includes a plurality of global bit lines and each one of the global bit lines is connected to a plurality of local bit lines, which are in turn connected to a plurality of memory cells. The apparatus includes a plurality of global bit line (GBL) latches and each GBL latch is located along a separate global bit line to latch a signal along the respective global bit line. The apparatus further includes a plurality of solar bit lines configured to connect the global bit lines to an output latch via a plurality of logic gates.

Increasing memory operating frequency

A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.

Port enable signal generation for gating a memory array device output

A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.

Jam latch for latching memory array output data

An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation.

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Westborough, MA, United States of America

Jigar Vora