Qualcomm Incorporated

Greater Shine Limited

Zeku Technology (shanghai) Corp., Ltd.

Sigma Designs, Inc.

Jifeng Geng

Daniel Fred Filipovic

Gary John Ballantyne

Hong Kui Yang

Christos Komninakis

Gurkanwal Singh Sahota

Bhushan Shanti Asuri

Jeremy Darren Dunworth

Gary J Ballantyne

Raghu Narayan Challa

Akash Kumar

Bo Sun

Insung Kang

Cristina A Seibert

Hung C Nguyen

Helena Deirdre O'Shea

Feng Wang

Ankit Maheshwari

Vijay Chellappa

Revathi Sundara Raghavan

Catherine A French

Qijia Liu

Ruoyang Lu

Niranjan Kumar Vadlamudi

Yanming Wang

Li Gao

A method and apparatus for wireless communication and storage medium are provided. The apparatus includes at least one processor; and memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: determine a guard band width associated with a symbol based on information about resource allocation to the apparatus; set a pulse-shaping parameter associated with the symbol based on the guard band width; and output the symbol having a waveform based on the pulse-shaping parameter.

Method and apparatus for wireless communication, and storage medium

Introduced here are techniques for reducing the average throughout of a baseband (BB)-radio frequency (RF) interface. The techniques include removing excess bits from a received signal based on the signal to noise ratio (SNR), rotating the reduced signal to direct current frequency, and applying a coding scheme to further compress the signal. After compression, the signal can be transmitted from one chip to another. The receiving chip can retrieve the signal by rotating the signal to its original frequency and retrieving the removed bits based uplink gain information. By doing so, the number of bits being transmitted is reduced and thus, the average throughput of the BB-RF interface is also reduced.

Power saving techniques for BB-RF interface

Embodiments of apparatus and method for digital variable gain adjustment (DVGA) are disclosed. In an example, a baseband chip includes an unpacking module, a symbol recording module operatively coupled to the unpacking module, and a first variable gain adjusting (VGA) module operatively coupled to the symbol recording module. The unpacking module is configured to unpack a plurality of symbols from a first representation of pseudo floating-point numbers to a second representation of fixed-point numbers. The symbol recording module is configured to obtain a symbol parameter based on the unpacking. The first VGA module is configured to dynamically adjust gains of the plurality of symbols having the second representation based on the symbol parameter.

Digital variable gain adjustment on baseband chip

Embodiments of apparatus and method for implementing weighted overlap-and-add (WOLA) after digital gain adjustment are disclosed. In an example, an apparatus for wireless communication includes a baseband chip and a radio frequency (RF) chip including a digital front-end. The baseband chip is configured to generate a stream of orthogonal frequency-division multiplexing (OFDM) symbols and adjust gains of the stream of OFDM symbols. The baseband chip or the RF chip is configured to apply WOLA to the stream of OFDM symbols having the adjusted gains.

Smooth orthogonal frequency division multiplexing symbols generation with varying gains

Embodiments of apparatus and method for generating waveforms for self-testing of radio frequency (RF) chips are disclosed. In an example, an RF chip includes an RF front-end and a digital front-end. The digital front-end includes an inverse fast Fourier transform (IFFT) module configured to generate at least one M-point IFFT sample, where M is a positive integer, and an IFFT sample transformation module configured to generate an L-point IFFT testing signal based on the at least one M-point IFFT sample. L is a positive integer greater than M and the L-point IFFT testing signal is configured to test a function of the RF chip.

Radio frequency chips having waveform generators for self-testing

Embodiments of apparatus and method for transition smoothing implementation on a stream of data are disclosed. In an example, a system on chip (SoC) for wireless communication includes a digital front-end. The digital front-end is configured to obtain a stream of data having one carrier or multi-carriers. The stream of data is divided into a plurality of blocks. The digital front-end is also configured to adjust a gain of the stream of data based on a predetermined frequency corresponding to a length of each of the plurality of blocks. The digital front-end is also configured to append a ramp-down tail sequence to a first block of the stream of data after a last sample of the first block, and generate a ramp-up head sequence for a second block immediately after the first block, based on a head sequence of the second block.

Smooth transition for data streams with adjusted gain

Methods, systems, and devices for wireless communications are described. The described methods, systems, and devices may include sampling an input signal to obtain one or more signal windows. An amplitude of a first sample within a first signal window of the one or more signal windows may be determined to exceed an amplitude threshold. A series of cancellation pulses may be combined with the first sample within the first signal window to obtain a reduced signal, the reduced signal including one or more reduced samples each having an amplitudes within the amplitude threshold. The series of cancellation pulses may be based on a characteristic of the first sample. The reduced signal may then be transmitted. The series of cancellation pulses may be based on, for example, an envelope of the first sample. In some cases, the series of cancellation pulses may be based on a phase of the first sample.

Techniques for successive peak reduction crest factor reduction

Certain aspects of the present disclosure generally relate to wireless communications. In some aspects, a device may determine a peak to average ratio (PAR) value for a portion of a wireless transmission. In some aspects, the device may cause, based on the PAR value, a voltage to be applied to a power amplifier of the device to cause the device to transmit the portion of the wireless transmission.

Techniques and apparatuses for peak to average ratio (PAR) based power management

Exemplary embodiments are related to method and devices for calibration a radio-frequency (RF) transceiver. A method may include calibrating an RF device by calculating input voltage values and bias voltage values of a power amplifier for each desired output voltage value of the power amplifier to generate a desired compression point. The method may also include applying digital pre-distortion (DPD) values to the input voltage of the power amplifier, and measuring a value of the output voltage after applying the DPD values.

Radio-frequency device calibration

Exemplary embodiments are related to power amplifier power level compensation in a pre-distortion system. A method may include applying digital pre-distortion (DPD) of a power amplifier at a frequency channel, a fixed input power value, and a fixed temperature. The method may also include determining an optimal input power value for the power amplifier in response to a change in at least one of frequency and temperature.

Power amplifier signal compensation

Aspects disclosed herein relate to predicting one or more signal characteristics to improve efficiency for a PA. A wireless communications device may be include a power amplifier and a processor that is associated with a signal prediction module. In an aspect, the processor may be a modem, a RF chip, etc. In one example, the wireless communications device may be configured to buffer one or more values associated with an input signal. The signal prediction module may be configured to predict a system response to at least a portion of the one or more buffered values, and generate a switcher control signal based on the system response. The signal prediction module may also generate a predicted supply voltage from the values associated with the input signal.

Method and apparatus for predicting signal characteristics for a nonlinear power amplifier

Circuitry for reducing power consumption is described. The circuitry includes a power amplifier. The circuitry also includes a predistorter coupled to the power amplifier. The circuitry further includes a power supply coupled to the power amplifier. The circuitry additionally includes a controller coupled to the power amplifier, to the predistorter and to the power supply. The controller captures a transmit signal and a feedback signal concurrently and determines a minimum bias voltage from a set of voltages and a predistortion that enable the power amplifier to produce an amplified transmit signal in accordance with a requirement.

Circuitry for reducing power consumption

Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.

Signal decimation techniques

A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

Phase locked loop with digital compensation for analog integration

A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).

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San Diego, CA, United States of America

Jifeng Geng