Canaan Creative Co., Ltd.

Globalfoundries Inc.

Canaan Creative (sh) Co., Ltd.

Jieyao Liu

Nangeng Zhang

Jingjie Wu

Shenghou Ma

Igor Arsovski

Wei Zhao

Qing Li

Xiaoli Hu

A clock generation circuit, a latch using same, and a computing device are provided. The clock generation circuit includes an input end, configured to input a pulse signal; a first output end, configured to output a first clock signal; a second output end, configured to output a second clock signal; and an input drive circuit, a latch circuit, an edge shaping circuit, a feedback delay circuit, and an output drive circuit, where the input drive circuit, the latch circuit, the edge shaping circuit, the feedback delay circuit, and the output drive circuit are sequentially connected between the input end and the first output end as well as the second output end in series. A clock pulse can be effectively shaped, the use of a clock buffer can be reduced, and the correctness and accuracy of data transmission and latching can be improved.

Clock generation circuit and latch using same, and computing device

The invention provides an on-chip passive power supply compensation circuit, and an operational unit, a chip, a hash board and a computing device using the same. The on-chip passive power supply compensation circuit comprises: two or more to-be-powered voltage domains, wherein the to-be-powered voltage domains are connected in series between a power supply and ground; and two or more isolation regions, wherein the to-be-powered voltage domains are formed in the isolation regions, and the isolation regions are configured for isolating the to-be-powered voltage domains; the isolation regions are connected in series between the power supply and the ground, wherein the on-chip passive power supply compensation circuit further comprises power supply compensation units connected between the to-be-powered voltage domains and the isolation regions for providing power supply compensation to the to-be-powered voltage domains.

On-chip passive power supply compensation circuit and operation unit, chip, hash board and computing device using same

The invention provides a full swing voltage conversion circuit. The full swing voltage conversion circuit comprises: an input terminal for inputting a first level signal; an output terminal for outputting a second level signal; a differential input unit for inverting the first level signal of the input terminal, and outputting a differential input signal; a conversion unit; and an output driving unit; wherein the full swing voltage conversion circuit further comprises an auxiliary pull-down unit between the input terminal and the conversion unit for receiving a feedback to improve capability of the conversion unit in recognizing the differential input signal, such that the full swing voltage conversion circuit of the invention can convert from inputting a low voltage to outputting a high voltage.

Full swing voltage conversion circuit and operation unit, chip, hash board, and computing device using same

The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

Dynamic D flip-flop, data operation unit, chip, hash board and computing device

The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.

Growing community of inventors

Beijing, China

Jieyao Liu