Spreadtrum Communications (shanghai) Co., Ltd.

Beijing Unisoc Communications Technology Co., Ltd.

Jiewei Lai

Kai Kang

Shusheng Guo

Junshi Qiao

Te Han

Yan Mei Zhang

Long Wang

Chinghwa Yu

Yexin Peng

Yiqiang Wu

Chaozhou Nan

Guobi Zhao

Beam detection method and device, beam adjusting method and device, antenna module selection method and device, and computer readable storage media are provided. The antenna module selection method is applied in a terminal device including first and second AiPs, and the method includes: the ULA array in the first AiP detecting signals emitted by the UPA array in the first AiP, and comparing detected characteristic parameter values of the signals emitted by the UPA array in the first AiP withe a first preset group of characteristics parameter values; the ULA array in the second AiP detecting signals emitted by the UPA array in the second AiP, and comparing detected characteristic parameter values of the signals emitted by the UPA array in the second AiP with a second preset group of characteristic parameter values: determining to use the first or second AiP for signal transmission and reception based on the comparison.

Beam detection method and device, beam adjusting method and device, antenna module selection method and device, and computer readable storage media

An antenna unit, an antenna system and an electronic device are provided. The antenna unit includes: a helical antenna with a three-dimensional structure, wherein the helical antenna is disposed on an edge region of a carrier board, and includes at least one turn of helical coil, wherein each of the at least one turn of helical coil includes multiple helical segments that are not in a same plane, and the multiple helical segments are respectively disposed in multiple layers of the carrier board. The antenna system includes a carrier board, a first antenna array and a second antenna array, wherein the first antenna array is disposed in a middle region of the carrier board and includes multiple patch units, the second antenna array includes at least one above antenna unit, and the helical antenna of the antenna unit is disposed at the edge region of the carrier board.

Antenna unit, antenna system and electronic device

An antenna sharing system and a terminal. The antenna sharing system comprises a communication module, and the communication module supports 5 GHz Wi-Fi and LTE. The antenna sharing system further comprises a first antenna and a first multiplexer; the first multiplexer at least comprises two multiplex input ends and a multiplex output end, a first multiplex input end of the first multiplexer is used for receiving and transmitting 5 GHz Wi-Fi secondary signals, a second multiplex input end of the first multiplexer is used for receiving and transmitting LTE secondary signals, and the multiplex output end of the first multiplexer is connected to the first antenna. The solution of the present invention can effectively improve the antenna utilization, and reduce the influences on data throughput of Wi-Fi and LTE while reducing the number of antennas.

Antenna sharing system and terminal

A patch antenna unit and an Antenna in Package (AIP) structure are provided. The patch antenna unit includes: a base substrate; multiple layers of patches stacked on the base substrate, wherein an isolation layer is disposed between adjacent layers of the patches, and configured to generate a radio frequency electromagnetic field, wherein an edge shape of at least one layer in the multiple layers of patches is a continuous and smooth function curve shape, and edge shapes of all sides of a same layer in the multiple layers of patches are a same function curve shape. Impedance bandwidth may be increased while symmetry of the antenna structure is maintained, and requirements of a substrate process are met, thereby increasing operation bandwidth of the AiP structure.

Patch antenna unit and antenna in package structure

Frequency multiplying circuit for clock signal is provided, including N branches and an N-times frequency multiplying circuit, wherein each branch includes a buffer and a frequency doubling circuit, and the frequency doubling circuit doubles a frequency of a reference clock signal to obtain a frequency doubled reference clock signal, wherein the N-times frequency multiplying circuit includes: N second calibration delay circuits coupled to the N frequency doubling circuits respectively, wherein each second calibration delay circuit performs clock delay on the frequency doubled reference clock signal to obtain a clock delayed frequency doubled reference clock signal; and an N-path phase combination circuit coupled to the N second calibration delay circuits, and configured to perform phase combination on the N clock delayed frequency doubled reference clock signals to obtain a 2N-times frequency multiplied reference clock signal. Cost is reduced, and phase noise of a multi-times frequency multiplied reference clock signal is optimized.

Frequency multiplying circuit for clock signal

A method for arranging a current source array of a DAC and a layout of a common-source current source array are provided in embodiments of the present disclosure for improving linearity and related performance of the DAC. The method includes, determining a number R of rows and a number C of columns of a common-source current source array; dividing the common-source current source array into M sub-arrays; segmenting the DAC to obtain (2&#x2212;1) groups of thermometer encoding current sources and Y groups of binary encoding current sources; arranging the (2&#x2212;1) groups of the thermometer encoding current sources into the M sub-arrays, arranging Y groups of binary encoding current sources into the M sub-arrays based on a number of binary encoding current sources in each of Y groups; arranging bias current sources evenly into the common-source current source array; and arranging other current sources as dummy cells.

Method for arranging current source array of digital-to-analog converter and layout of common-source current source array

An RC oscillator is provided for improving stability of oscillation frequency. The circuit includes an input module, an oscillating module, an inverting module, first and second compensating modules and an output module, wherein the input module provides two-path charging currents and bias current for the oscillating module; the oscillating module outputs a first high level or a first low level to the inverting module under the control of the two-path charging currents and bias current, and improves frequency tuning accuracy of the oscillator; the inverting module inverts the first high level to a second low level or inverts the first low level to a second high level, and outputs the second low level or the second high level to the output module; the output module outputs the second high level and the second low level; and the first and second compensating modules improve stability of the oscillation frequency.

Resistor-capacitor oscillator

A latch and a frequency divider are provided. The latch includes: a first logic unit coupled between a power supply and a ground wire, wherein the first logic unit includes a first input terminal and a first output terminal; a second logic unit having a structure symmetrical to that of the first logic unit, wherein the second logic unit includes a second input terminal and a second output terminal; and a first feedforward control unit adapted for cutting off a first current path, wherein the first feedforward control unit includes a first clock signal input terminal adapted for receiving a first clock signal, a third output terminal coupled to the first output terminal, and at least two feedforward control terminals, at least one of which is coupled to the first input terminal or the second input terminal. Power consumption of the latch and the frequency divider can be reduced.

Latch and frequency divider

A signal transceiver is provided. The signal transceiver includes: signal convert circuit adapted to convert single-ended signals into differential signals; first power amplifier; receiving amplifier; impedance convert circuit; first capacitive circuit; second capacitive circuit; and first switch circuit; wherein output terminals of the signal convert circuit are connected with output terminals of the first power amplifier and first set of terminals of the first capacitive circuit; second set of terminals of the first capacitive circuit is connected with first set of terminals of the impedance convert circuit; second set of terminals of the impedance convert circuit is connected with input terminals of the receiving amplifier and first set of terminals of the second capacitive circuit; second set of terminals of the second capacitive circuit is connected with first set of terminals of the first switch circuit; and second set of terminals of the first switch circuit is connected to ground.

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Shanghai, China

Jiewei Lai