Micron Technology Incorporated

Jiewei Chen

Jordan D Greenlee

John David Hopkins

Nancy M Lomeli

Rita J Klein

Shuangqiang Luo

Xiao Li

Mithun Kumar Ramasahayam

Indra V Chary

Tomoko Ogura Iwasaki

Silvia Borsari

Vinayak Shamanna

Jun Fang

Kaiming Luo

Vladimir Samara

Allen McTeer

June Lee

John Mark Meldrim

Everett Allen McTeer

Collin Howder

Alyssa N Scarbrough

David Ross Economy

Jivaan Kishore Jhothiraman

Yiping Wang

Luyen Tien Vu

Tracy D Evans

Shen Hu

Gloria Yang

Chieh Hsien Quek

Naiming Liu

Everett A Mcteer

Jing Zhou

Aaron P Thurber

Sijia Yu

Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel material strings extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair step region comprises a cavity comprising a flight of stairs having insulative material atop stair treads. Individual of the treads comprise conducting material of a conductive tier. Conductive vias extend through the insulative material and are directly above and against the conducting material of the respective individual tread. A lining is over sidewalls and bottom of the individual conductive vias. The individual conductive vias are directly under the bottom of the lining directly above the conducting material of the respective individual tread. Other embodiments, including methods of forming the circuitry and elements of circuitry above, are disclosed.

Memory circuitry and method used in forming memory circuitry

A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

Methods used in forming a memory array comprising strings of memory cells and memory arrays comprising strings of memory cells

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a first vertical stack comprising vertically-alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. A second vertical stack is aside the first vertical stack. The second vertical stack comprises insulative tiers collectively comprising at least two different compositions relative individual of the insulative tiers. Individual of the at least two different compositions comprise silicon nitride. One of the individual different compositions comprise carbon-doped silicon nitride having at least 0.5 atomic percent more carbon than atomic percent of carbon, if any, in the silicon nitride of another of the individual different compositions. Other embodiments, including method, are disclosed.

Methods used in forming memory arrays having strings of memory cells

Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

Dynamic latches above a three-dimensional non-volatile memory array

A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A lining is formed in and that less-than-fills the cavity atop treads of the stairs. Individual of the treads comprise conducting material of one of the first tiers in the finished-circuitry construction. The lining that is atop the treads is replaced with at least one of metal material, polysilicon, or SiGe and insulative material is provided in remaining volume of the cavity directly above the at least one of the metal material, the polysilicon, or the SiGe. Conductive vias are formed through the insulative material and the at least one of the metal material, the polysilicon, or the SiGe. Individual of the conductive vias are directly above and directly against the conducting material of one of the individual treads. Other embodiments, including structure, are disclosed.

A microelectronic device includes a stack structure, slot structures, and dielectric material. The stack structure includes blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. At least one of the blocks includes an array region including strings of memory cells, and a staircase region including a crest sub-region interposed between a staircase structure and the array region. An uppermost boundary of the tiers within the crest sub-region underlies an uppermost boundary of the tiers within the array region. The slot structures are interposed between the blocks of the stack structure. The dielectric material extends over and between the blocks of the stack structure. A thickness of a portion of the dielectric material overlying the crest sub-region is greater than a thickness of an additional portion of the dielectric material overlying the array region. Related memory devices, electronic systems, and methods are also described.

Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems

A method used in forming a memory array comprising strings of memory cells comprises forming memory block regions individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a void-space extending laterally-across individual of the memory-block regions. At least one of conductive or semiconductive material is formed in the void-space laterally-outward of individual of the channel-material strings. Conductive molybdenum-containing metal material is formed in the void-space directly against the at least one of the conductive or the semiconductive material and a conductive line comprising the conductive molybdenum-containing metal material is formed therefrom. The at least one of the conductive or the semiconductive material is of different composition from that of the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.

Creating dynamic latches above a three-dimensional non-volatile memory array

Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

Systems associated with device temperature adjustment are described. A device temperature adjustment system can include an electronic device having a temperature sensor integrated therein to detect a temperature of the electronic device and a temperature adjust module coupled to the electronic device to adjust a temperature of the electronic device based on the detected temperature.

Device temperature adjustment

A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.

Methods used in forming a memory array comprising strings of memory cells

An electronic device comprises a stack structure comprising tiers of alternating conductive structures and insulative structures, staircase structures within the stack structure and including steps defined by edges of the tiers, contacts on the steps of the staircase structures, support pillars extending vertically through the stack structure, and support structures laterally adjacent to the contacts in a first horizontal direction and extending vertically through the stack structure. The support pillars exhibit a lateral dimension relatively larger than a lateral dimension of the contacts and the support structures. Related methods, memory devices, and systems are also described.

Electronic devices including stair step structures, and related memory devices, systems, and methods

A method of forming a microelectronic device comprises forming a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures. Apertures are formed to extend to surfaces of the insulative structures at different depths than one another within the stack structure. Dielectric liner structures are formed within the apertures. Sacrificial structures are formed within portions of the apertures remaining unoccupied by the dielectric liner structures. Upper portions of the sacrificial structures are replaced with capping structures. Portions of the insulative structures and remaining portions of the sacrificial structures are replaced with electrically conductive material. Microelectronic devices and electronic systems are also described.

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Boise, ID, United States of America

Jiewei Chen