Cirrus Logic Inc.

Jieren Bian

Zhong You

Jeffrey Allen May

Graeme Gordon Mackay

Jeff W Baumgartner

Hua Hong

A distributed network system may include a shared communication bus that operates in accordance with a communication protocol and a plurality of devices coupled to the bus. In accordance with the communication protocol, when one or more of the plurality of devices is actively transmitting data on the bus, each of the plurality of devices receives data via the bus such that bidirectional communication is established among the plurality of devices via the bus, each of the plurality of devices monitors a bus state of the shared communication bus to avoid data contention and to synchronize receipt of encoded symbols and encoded messages comprising encoded symbols via the bus, and each actively transmitting device of the plurality of devices compares the bus state to a desired state of such actively transmitting device to determine a priority among actively transmitting devices of the plurality of devices with respect to the bus.

Encoding for multi-device synchronization of devices

An apparatus and a method for clock mode determination utilizing SCLK auto-detection and generation circuitry at a serial port which has a reduced number of pin-count by eliminating the need for inputting a master input clock signal MCLK and/or a serial input clock signal SCLK. The SCLK auto-detection and generation circuitry includes a SCLK detector circuit, a serial mode detector circuit, an internal SCLK generator circuit, a multiplexer, and an edge detector circuit. The SCLK detector circuit is used to detect whether an external serial clock signal is present and to generate a selection signal. The serial mode detector is used to detect whether an incoming data signal is in a non-TDM mode or a TDM mode and to generate a mode signal.

SCLK auto-detection and generation in various serial port modes

A signal processing system includes a phase-locked loop to provide an output signal used, for example, as a delta sigma modulator operating clock signal. In at least one embodiment, a frame clock that provides synchronization for one or more blocks of data is used by the phase-locked loop as a reference signal. Utilizing the frame clock as the reference signal allows the signal processing system to reduce the number of clock signals present in the signal processing system. In another embodiment, a phase-locked loop includes a loop filter that utilizes a sample and reset circuit, a feed forward integrator, and a feed forward stabilizer to provide a low frequency phase-locked loop bandwidth. In at least one embodiment, the feed forward integrator amplifies capacitance of the sample and reset circuit, which reduces the size of loop filter capacitors and, thus, allows on-chip capacitor integration.

Growing community of inventors

Austin, TX, United States of America

Jieren Bian