National Yang Ming Chiao Tung University

National Science Council of Republic of China

Taiwan Semiconductor Manufacturing Comp. Ltd.

National Science Council

Global Unichip Corporation

Century Semiconductor, Inc.

Jieh-Tsorng Wu

Ting-Hao Wang

Hsie-Chia Chang

Chin-Chieh Chao

Wei-Hsin Tseng

Hsi-Yuan Wang

Ta-Hui Wang

Chun-Cheng Huang

Keh-Yung Tso

Tsen-Shau Yang

Ju-Ming Chou

Yu-Tang Hsieh

Jen-Lin Fan

Wer-Jen Chen

Chung-Yi Wang

Jeng-Long Hsu

A calibration system includes a jitter-capturing analog-to-digital converter (ADC), a calibration value generating circuit and a first calculation circuit. The jitter-capturing ADC is configured to sample a to-be-sampled clock signal according to an operating clock signal to generate a first quantized output. The calibration value generating circuit is configured to receive the first quantized output and a second quantized output of a to-be-calibrated ADC to generate a calibration value. The operating clock signal is for driving the to-be-calibrated ADC to sample, and the calibration value is related to a phase noise of the operating clock signal. The first calculation circuit is coupled with the calibration value generating circuit, and configured to subtract the calibration value from the second quantized output to generate a third quantized output.

Calibration system of canceling effect of phase noise and analog-to-digital converting device comprising the same

An N-bit digital-to-analog converting device includes: a decoder for converting an N-bit binary digital signal into a multi-bit thermometer code during each cycle of a clock signal alternating between first and second states, N being an integer not less than two; a random number generator for generating a reset signal having at least one high logic level bit and at least one low logic level bit that are equal in number and that have a random, time-varying arrangement; and a converting module coupled electrically to the decoder and the random number generator, and configured to convert the thermometer code into an analog voltage corresponding to the digital signal when the clock signal is in the first state, and to reset the analog voltage to a reset value according to the reset signal when the clock signal is in the second state.

N-bit digital-to-analog converting device

The present invention discloses a background calibration system and method for calibrating the non-linear distortion of the amplifier. The calibration method in the present invention includes: generating random sequences and inputting the random sequences in different amount and different sets into an amplifier; amplifying the random sequences and detecting linear and non-linear coefficients; quantizing the output linear signal from the amplifier, and generating a digital output signal; multiplying the digital output signal to generate a high-order signal; generating an estimated non-linear error for the amplifier by multiplying the high-order signal with the estimated non-linear coefficient; adding the non-linear signal with the digital output signal to generate a linear output signal; calculating the random value from the parameter extractor to determine the occurrence of non-linear distortion in the circuit, and further adjusting the non-linear coefficient to calibrating the amplifier.

Background calibration system for calibrating non-linear distortion of amplifier and method thereof

An analog-to-digital converter (ADC) having a two-channel or multi-channel structure processes background timing calibration. Signals from the ADC are directly compared for the calibration. Additional signal or interruption of circuit is not required. A dynamic calibration is processed. A timing-skew error is kept in a low level and a process mismatch is not a concern. Moreover, sampling frequency and input signal frequency are improved. A high sampling frequency and a high speed of signal inputting are achieved; and chip area can be greatly shrunk because the extra calibration circuits are simple digital circuits.

Time-interleaved analog-to-digital converter having timing calibration

A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.

Method of combining multilevel memory cells for an error correction scheme

A background-calibrated comparator and a background-calibrated flash analog-to-digital converter are disclosed for using in mixed-signal integrated circuit design in particular on the high-speed analog-to-digital converter circuit. Without affecting the operation of the comparator, the disclosure is directed at reducing the unpredictable input offset voltage originated from the variation of process parameters and environmental factors. The background-calibrated comparator includes a random chopping comparator, a calibration processor, and a random sequence generator. The background-calibrated flash analog-to-digital converter (ADC) includes a background-calibrated comparator array together with a reference voltage generator, a thermometer code edge detector, and a set of digital encoders.

Background comparator offset calibration technique for flash analog-to-digital converters

A digital FM demodulator utilizes delay lines as the timing reference and incorporates the concept of delta-sigma analog-to-digital conversion to implement the function of time-to-digital conversion. The FM demodulator is constructed from delay lines, a multiplexer, a phase detector, a charge pump circuit, a quantizer and a digital integrator. The modulated signal on an intermediate frequency carrier passes through the delay lines and is then phase-compared with the original modulation signal. The comparison produces a pulse which is converted into a voltage and stored in a capacitor by way of the charge pump circuit. The voltage having been accumulated and quantized, a new delayed output signal is acquired to compare its phase with the input signal. Meanwhile, the phase difference between input signal and delayed signal is used to select a delay for the delayed signal for the next cycle. The phase difference is continuously evaluated and adjusted to produce zero phase difference. The digital modulation signal is collected at the system output.

Digital FM demodulator with reduced quantization noise

To reduce the effect of the phase shift error originated from the mismatch of the delay units of the clock generator, we propose to add one more set of averaging amplifiers and averaging impedances, such as resistors, into the circuit of the clock generator. In the clock generator, outputs of all delay units connect to inputs of all averaging amplifiers respectively, and the averaging impedances connect the corresponding outputs of two adjacent averaging amplifiers, so as to form a closed loop. When a phase shift error occurs in the delay units, the averaging current through the averaging impedances will decrease the phase shift error in each stage. Specifically, the output impedance of the averaging amplifiers approaches infinite, and thus the resistance of the averaging impedances is relatively small. Therefore almost all signal currents will go through the averaging impedances, and an optimal averaging effect is achieved. In addition, we apply the simple voltage-mode phase interpolation technique to the averaging impedances for better phase resolution and more output phases. Further, utilizing the folding architecture, our proposed clock generator can output high-frequency clock signals at low-frequency operating clock.

Clock generator

An interpolating D/A converter architecture includes a reference voltage generator, a decoding switch network, a routing switch, and an interpolating buffer. The reference voltage generator generates a plurality of reference voltages. The decoding switch network is coupled to the reference voltage generator for selecting two reference voltages from the plurality of reference voltages in response to the plurality of high bits of digital video signals. The routing switch is coupled to the decoding switch network for selectively providing a first reference voltage and a second reference voltage in response to a plurality of low bits of the digital video signals. And the interpolating buffer is coupled to the routing switch for outputting an interpolated analog signal in response to the first reference voltage and the second reference voltage. Eventually, the present invention can save half the D/A reference lines and half the associated decoding switch rows, and thereby save the die cost.

Interpolating digital to analog converter and TFT-LCD source driver using the same

A frequency synthesizer using a multiphase reference signal source consists of three portions: a basic phase locked loop including a variable frequency oscillator, a loop filter, a phase detector, and a frequency divider; a generating circuit including a multiphase reference signal source for providing a reference signal to the basic phase locked loop; and a frequency discriminator and phase modulator. The frequency discriminator facilitates detection of whether the main loop of the frequency synthesizer is approaching a phase locking state for a proper change of the loop bandwidth. The phase modulator is employed to change the output phase of the reference signal source in order to speed up phase locking and make it applicable to creating signals with a rapid frequency switching speed, frequency tuning capability, and fine channel resolution.

Frequency synthesizer accomplished by using multiphase reference signal source

An active pixel sensor is used to replace a charge coupled device (CCD) image sensor. The active pixel sensor may be operated in a low voltage environment and the power consumption is lower than that in the conventional CCD image sensor and the CMOS active pixel sensor which is now developed by current industry. The active pixel sensor of the present invention has a lower cost and may be applied to a portable system.

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Hsinchu, Taiwan

Jieh-Tsorng Wu