Taiwan Semiconductor Manufacturing Comp. Ltd.

Jieh-Jang Chen

Feng-Jia Shiu

Wei-Chieh Huang

Ching-Sen Kuo

Shih-Chi Fu

Chin-Wei Liang

Gwo-Yuh Shiau

Chia-Shiung Tsai

Chern-Yow Hsu

Cheng-Che Chung

Tsai-Ming Huang

Chia-Tung Ho

Feng-Jia Shih

Hsia-Wei Chen

Sheng-Chau Chen

Hsun-Chung Kuang

Yuan-Hung Liu

Yen-Chang Chu

Chih-Ta Wu

Hung Chang Hsieh

Chern-yow Hsu

Chia-Shiung Tsia

Yeur-Luen Tu

Chia-Hua Chu

Shih-Wei Lin

Chi-Hsin Lo

Kuo-Yin Lin

Yi Jen Tsai

Hsing-Fei Chou

Shun-Wei Lan

Chien Hsien Tseng

In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.

Semiconductor device and methods of manufacturing thereof

A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

Via structure and methods of forming the same

A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.

Method of forming a bottom electrode of a magnetoresistive random access memory cell

VIA structure and methods of forming the same

In a method of manufacturing a semiconductor device, a first layer having an opening is formed over a substrate. A second layer is formed over the first layer and the substrate. A photo resist pattern is formed over the second layer above the opening of the first layer. The photo resist pattern is reflowed by a thermal process. An etch-back operation is performed to planarize the second layer.

Method for manufacturing a semiconductor device

A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.

Method for manufacturing semiconductor device

A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed.

Methods of forming semiconductor structures

Growing community of inventors

Hsinchu County, Taiwan

Jieh-Jang Chen