Taiwan Semiconductor Manufacturing Comp. Ltd.

Jiech-Fun Lu

Yeur-Luen Tu

Shih-Pei Chou

Hung-Wen Hsu

Chia-Shiung Tsai

Tsun-Kai Tsao

Ching-Chung Su

Cheng-Hsien Chou

Chun-Tsung Kuo

Yu-Hung Cheng

Shu-Ting Tsai

Cheng-Ta Wu

Shih Pei Chou

Shih-Chang Liu

Chih-Yu Lai

Wen-I Hsu

Yen-Shuo Su

U-Ting Chen

Po-Han Huang

Hsiu-Yu Cheng

Kuan-Liang Liu

Chun-Han Tsao

Yu-Chun Chen

Ming Chyi Liu

Yu-Lung Yeh

Hung-Ling Shih

Wei Chuang Wu

Jian Yuan Wu

Ming-Chi Wu

Kuo-Hwa Tzeng

Chi-Yuan Wen

Chia-Chieh Lin

Chun-Chieh Fang

Tzu-Ming Wang

Che-Hsiang Hsueh

Min-Feng Kao

Feng-Chi Hung

Min-Ying Tsai

Chen-Fa Lu

Jung-I Lin

Ching-Chun Wang

Jhy-Jyi Sze

Shyh-Fann Ting

Chun-Wei Chang

Keng-Ying Liao

Yung-Lung Lin

Wei-Li Huang

Po-Zen Chen

Ching I Li

Yi-Hung Chen

Wang-Pen Mo

Kai Tzeng

Tung-Ting Wu

Tzu-Hsiang Chen

Chung-Bin Tseng

Chung Chien Wang

Wei-Lin Chen

Chiao-Chun Hsu

Chun-Mao Chiu

Tao-Sheng Chang

Wei-Chuang Wu

Li-Weng Chang

Ming-I Wang

Kuan Chih Huang

Tze Yun Chou

Lin Chia-Chieh

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a mask layer on a first side of a semiconductor substrate. The mask layer comprises a plurality of sidewalls defining a plurality of openings. A first etch process is performed on the semiconductor substrate to form a plurality of recesses within the semiconductor substrate. A second etch process is performed on the semiconductor substrate to expand the plurality of recesses and form a plurality of protrusions that comprise curved opposing sidewalls.

Absorption enhancement structure to increase quantum efficiency of image sensor

Various embodiments of the present disclosure are directed towards an integrated chip including an optical device within or on a semiconductor substrate. A light guide structure overlies the optical device. A first etch stop layer extends along first sidewalls and a lower surface of the light guide structure. A second etch stop layer overlies the first etch stop layer and extends along second sidewalls of the light guide structure.

Method for forming light pipe structure with high quantum efficiency

Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a plurality of photodetectors disposed within a substrate, and the plurality of photodetectors includes a first active photodetector and a black level correction (BLC) photodetector. A metal grid structure surrounds the first active photodetector along a periphery of the first active photodetector on a first side of the substrate. A recessed blocking structure covers the BLC photodetector on the first side of the substrate. The recessed blocking structure includes both a first blocking layer inset into the first side of the substrate and a second blocking layer directly over the first blocking layer.

Recessed blocking structure for BLC pixels

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first bond pad isolation structure within a substrate. A second bond pad isolation structure is formed with the substrate. The second bond pad isolation structure is disposed laterally between inner sidewalls of the first bond pad isolation structure. The first bond pad isolation structure and the second bond pad isolation structure are formed concurrently with one another. A bond pad is formed extending through the substrate. The bond pad comprises a conductive body overlying the second bond pad isolation structure and a conductive protrusion extending from the conductive body to below the substrate. The second bond pad isolation structure laterally wraps around the conductive protrusion.

Bond pad structure with reduced step height and increased electrical isolation

A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.

Self aligned grids in BSI image sensor

In some embodiments, the present disclosure relates to an integrated chip (IC). The IC includes a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate. An insulating structure is disposed along inner sidewalls of the semiconductor substrate. The inner sidewalls of the semiconductor substrate extend through the semiconductor substrate. A blocking layer is disposed along inner sidewalls of the insulating structure. A through-substrate via (TSV) includes a first portion and a second portion. The first portion extends from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure. The second portion extends from the first portion to the conductive structure and has a maximum width less than that of the first portion.

Through-substrate via formation to enlarge electrochemical plating window

Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Method for forming a semiconductor-on-insulator (SOI) substrate

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a resistive structure overlying the substrate. The resistor also comprises a conductive contact overlying and electrically coupled to the resistive structure. A capping structure is disposed over the conductive contact, wherein the capping structure extends laterally over an upper surface of the conductive contact and vertically along a first sidewall of the conductive contact, such that a lower surface of the capping structure is disposed below a lower surface of the conductive contact.

Method (and related apparatus) for forming a resistor over a semiconductor substrate

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes depositing a resistive layer over a substrate. A conductive structure is formed over the resistive layer. A first etch process is performed on the resistive layer to define a resistor segment of the resistive layer and a peripheral region of the resistive layer. The resistor segment is laterally separated from the peripheral region of the resistive layer. The peripheral region continuously laterally wraps around an outer perimeter of the resistor segment.

Ring structure for film resistor

Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a substrate. The substrate has a front-side surface and a back-side surface. An absorption enhancement structure is disposed along the back-side surface of the substrate and overlies the photodetector. The absorption enhancement structure includes a plurality of protrusions that extend outwardly from the back-side surface of the substrate. Each protrusion comprises opposing curved sidewalls.

Various embodiments of the present disclosure are directed towards a semiconductor structure including a photodetector disposed within a substrate. A grid structure is disposed over the substrate and the photodetector. A conductive layer is disposed between the grid structure and the substrate. A conductive contact extends into an upper surface of the substrate. The conductive layer is directly electrically coupled to the conductive contact.

Charge release layer to remove charge carriers from dielectric grid structures in image sensors

In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.

Concave reflector for complementary metal oxide semiconductor image sensor (CIS)

A backside illumination (BSI) image sensor and a method of forming the same are provided. A device includes a substrate and a plurality of photosensitive regions in the substrate. The substrate has a first side and a second side opposite to the first side. The device further includes an interconnect structure on the first side of the substrate, and a plurality of recesses on the second side of the substrate. The plurality of recesses extend into a semiconductor material of the substrate.

BSI image sensor and method of forming same

The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

Back-side deep trench isolation structure for image sensor

Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

Method for forming thin semiconductor-on-insulator (SOI) substrates

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Madou, Taiwan

Jiech-Fun Lu