Shanghai Ic R&d Center Co., Ltd

Chengdu Image Design Technology Co., Ltd.

Shanghai Integrated Circuit Equipment & Materials Industry Innovation Center Co., Ltd

Jiebin Duan

Pengfei Wang

Chen Bo Li

Yu Jiang

Jianxin Wen

Tao Zhou

Ling Shen

Hao Fu

Huijie Yan

Zheng Ren

Changming Pi

Lingyi Guo

Yan Yan

Zhifang Li

Xueru Yu

Xiucui Wang

Liren Li

Chen Li

Bowen Xu

Linmei Dong

Hongxia Sun

The present invention disclosures a memory array structure, comprising an array composed of multiple memory devices arranged in rows and columns, each of the rows is set with a row leading-out wire, and each of the columns is set with a column leading-out wire, memory devices are correspondingly positioned at intersection points of each row leading-out wire and each column leading-out wire; wherein, the first terminal of each of the memory devices is individually connected to the row leading-out wire of the same row, and the second terminal of each of the memory devices is connected to a first terminal of a switch in the same column, the second terminal of the switch is connected to the column leading-out wire of the same column; wherein, each of the rows is set with one to multiple the switches, and the first terminal of each of the switches is connected to one to all of the second terminals of the memory devices in the same column. The advantage of the present invention is that the corresponding analog currents output of input signals of different specified rows according to multiply-accumulate operation requirements of each of the columns can be obtained simultaneously, thus multiply-accumulate operations of different input signals of different scales can be performed, which greatly improves operation speed and using efficiency of the array.

Memory array structure

The present invention disclosures a critical dimension error analysis method, comprising: S: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S: removing extreme outliers from the critical dimension (CD) values; S: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD″) values, according to relative error between CD″ and CD, dividing the rebuilt critical dimension (CD″) values into scenes and the number of the scenes is A; S: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S: modifying machine parameters and masks by the correction model according to above calculation results. The present invention uses an outer limit to remove extreme outliers, so as to analyze a critical dimension error during a lithography process quickly and accurately.

Critical dimension error analysis method

The present invention discloses a pixel structure of a stacked image sensor and a preparation method thereof, by bonding processes to stack a first silicon wafer to a third silicon wafer up and down; wherein, a first photodiode array is set on the first silicon wafer located in middle, and a second photodiode array is provided on the second silicon wafer located above, and the surface of each the second photodiode in the second photodiode array is aligned and bonded correspondingly with the surface of each the first photodiode in the first photodiode array, so as to form a chip of the pixel structure of the stacked image sensor with a very deep junction depth, which is particularly suitable for near-infrared sensitization, and can effectively improve quantum efficiency in near-infrared wave bands; and by adopting a backlight technology, incident lights irradiating to photodiodes are not affected by the metal interconnect layers, both of sensitive and fill factor are high, especially for small-size pixels, which has very good photosensitive performance, so as to balance the near-infrared quantum efficiency and the small pixel size.

Pixel structure of stacked image sensor and preparation method thereof

The present invention discloses an image sensor for real-time calibration of dark current, including a pixel array comprises at least a pixel unit, the pixel unit includes a pixel photosensitive portion, a pixel dark shielding portion and a subtraction circuit, photodiodes in the pixel photosensitive portion and the pixel dark shielding portion are isolated by deep trench isolations, the pixel dark shielding portion are covered by a dark shielding layer; both of the pixel photosensitive portion and the pixel dark shielding portion adopt a same voltage and sequential control, a light ambient voltage signal and a non-light ambient voltage signal are generated and connected to both ends of a subtraction circuit to realize subtraction and dark current calibration. The present invention discloses an image sensor for real-time calibration of dark current, which can make the dark current calibration completed directly within the pixel, and can better cover the dark pixel part, so as to make calibration value of dark current and dark noise more accurate.

Image sensor for real time calibration of dark current and calibration method

The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.

Global shutter CMOS pixel circuit and image capturing method thereof

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Shanghai, China

Jiebin Duan