Philips Electronics North America Corporation

Koninklijke Philips Corporation N.v.

Jie Zheng

Neil Edward Birns

William J Slivkoff

Hong Bin Hao

Richard Fabbri

William W Kolb

Hartmut Karl Habben

A CAN microcontroller that supports a plurality of uniquely-numbered message objects, that includes a processor core that runs CAN applications, a plurality of message buffers associated with respective ones of the message objects, and a CAN/CAL module. The CAN microcontroller further includes a plurality of individual message object registers associated with each message object, including at least one control register that contains an interrupt-enable control bit, a receive enable bit, and a transmit enable bit. The CAN microcontroller also includes a plurality of global message object control registers, including at least one message complete status register that contains a plurality of status flag bits for respective ones of the message objects, at least one interrupt flag register that contains a receive complete interrupt flag bit and a transmit complete interrupt flag bit, and a message complete info register that contains a plurality of message object identification bits and a status bit. The CAN/CAL module includes a message handling function that automatically transfers successive frames of an incoming multi-frame message to the message buffer associated with a corresponding message object; an end-of-message detection function that detects an end-of-message condition which occurs when the last frame of the accepted incoming multi-frame message has been stored in the message buffer associated with the corresponding message object; and, an end-of-message detection handling and interrupt generation function that, in response to the detection of the end-of-message condition: sets the status flag bit contained in the at least one message complete status register associated with the corresponding message object; sets the receive complete interrupt flag bit contained in the at least one interrupt flag register, if the interrupt-enable control bit contained in the at least one control register associated with the corresponding message object is set; and, sets the status bit contained in the message complete info register, if the interrupt-enable control bit contained in the at least one control register associated with the corresponding message object is set.

End-of-message handling and interrupt generation in a CAN module providing hardware assembly of multi-frame CAN messages

A reset device is disclosed which is part of a micro-controller formed on an integrated circuit. The reset device has a counter which outputs a count enable signal after counting a predetermined number of counts. In response to an input reset signal, an input device of the reset device provides a start signal to the counter for initiating count-down thereof. An output device outputs an output reset signal in response to the start signal and the count enable signal. The start signal is inhibited by a control signal, which is provided from a control device in response to an external reset signal received at an input pin of the micro-controller. The input device includes an AND gate which receives the input reset signal, an inverted delayed version of the input reset signal, and the disable signal. The reset device further includes an OR gate which receives the start signal and the count enable signal to provide an input signal to the output device for generation of the output reset signal. Another OR gate receives the outputs the counter and provides the count enable signal.

Reset-out circuit with feed back capability

A FIFO unit for buffering serial communications includes a register and a unit for maintaining a single pointer. The single pointer functions as an IN pointer during writes and an OUT pointer during reads. The same circuitry maintains the pointer for both reads and writes to the FIFO. This circuitry preferably includes a single counter. If an error occurs during reading, the single pointer can be reinitialized and reading restarted, without loss of data. The register is not erased until reading is complete.

FIFO unit with single pointer

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Mountain View, CA, United States of America

Jie Zheng