International Business Machines Corporation

Cofco Limited

Siemens Aktiengesellschaft

Novozymes Als

Norozymes Als

Jie Zheng

Steven R Carlough

Stephen J Powell

Susan M Eickhoff

Patrick James Meaney

Gary A Van Huben

Raymond Wong

Warren Edward Maule

Jeffrey M Turner

Howard M Haynie

Mushfiq U Saleheen

Kunwadee Sripanidkulchai

Donald Jung

William John Starke

Jeffrey A Stuecheli

Sambit Sahu

Michael James Becht

Andrew R Ranck

Patrick B Heywood

Haiyu Ren

Hong Zhi Huang

Murthy V Devarakonda

Xin Xu

Yao Liang Chen

Deanna Postles Dunn Berger

Anees Abdul Shaikh

Chitra Dorai

Clinton E Bubb

Jeffrey C Hanscom

Chad G Wilson

Hai B Zou

Ying-Yeung Li

Andreas Kohler

James F Driftmyer

Sean Donnellan

De Shou Kong

Yuen C Tschang

Poornima P Sulibele

Xiang Deng

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.

Host synchronized autonomous data chip address sequencer for a distributed buffer memory system

Aspects of the invention include computer-implemented methods, systems, and computer program products that assign a centralized event tag to each communication interface of a plurality of communication interfaces of a chip interconnected in a hierarchy through the communication interfaces to a plurality of chips in a multiprocessing system. A determination is performed of whether to accept or drop a message associated with an event received at one of the communication interfaces of the chip based on comparing a local centralized event tag with a received centralized event tag. The local centralized event tag is updated based on one or more advancing rules to maintain event synchronization between the chip and the plurality of chips.

System event broadcast synchronization across hierarchical interfaces

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

Address/command chip controlled data chip address sequencing for a distributed memory buffer system

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.

Speculative bank activate dynamic random access memory (DRAM) scheduler

Technical solutions are described for computing data check word for a host request for an I/O processing operation at a host computer system that communicates with a control unit. An example method includes obtaining information for a first I/O operation at a channel subsystem in the host computer system, and accessing an address control word (ACW) of the first I/O operation. The ACW is stored in the local channel memory, and the ACW includes a first data check seed-value. The method also includes computing a first data check word based on the first data check seed-value from the ACW. The method also includes obtaining information for a second I/O operation at the channel subsystem, and in response to the second i/o operation corresponding to said ACW of the first I/O operation, computing a second data check word based on a second data check seed-value from a cache memory.

Predictive caching for check word snooping in high performance ficon

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one aspect, the data buffer circuit receives a next to be used store data tag from a Host wherein the store data tag specifies the data buffer location in the data buffer circuit to store data, and in response to receiving store data from the Host, moves the data received at the data buffer circuit into the data buffer pointed to by the previously received store data tag.

Host controlled data chip address sequencing for a distributed memory buffer system

An Address and Command chip of a distributed memory system includes a memory controller, a first communication link, and one or more interface schedulers, where the one or more interface schedulers include a first interface scheduler residing communicatively between the memory controller and the first communication link. The first interface scheduler is configured to receive a first communication directed from the memory controller to the first communication link; capture the first communication before the first command reaches the first communication link; postpone the first communication for a first set of one or more memory cycles; and reissue the first communication to the first communication link in association with a first cycle offset code indicating how many memory cycles the first command was postponed.

Interface scheduler for a distributed memory system

Examples of techniques for hang detection and recovery are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: sending, by a processor, a read request to a controller; detecting, by a data hang detection circuit, the read request; initiating, by the data hang detection circuit, a counter when the read request is first detected; monitoring, by the data hang detection circuit, to receive a read response from the controller; and responsive to the counter reaching a timeout threshold before receiving the read response, sending, by the data hang detection circuit a timeout error to the processor via a multiplexer in the data hang detection circuit.

Hang detection and recovery

A method for updating a descriptor engine for a network interface card (NIT) can include quiescing, by a processing device, a transmit stream to the NIC. The method can further include stopping, by the processing device, a descriptor engine from providing new receive descriptors to the NIC. The method can further include setting, by the processing device, a controller to redirect inbound traffic to the memory. The method can further include restoring, by the processing device, a transmit configuration and a transmit state of the descriptor engine subsequent to updating the descriptor engine.

Upgrading a descriptor engine for a network interface card

The present invention provides a method and system for receiving by a user from a source a communication being a fragment of a message having an unrecognizable part containing confidential data. The unrecognizable part is converted into recognizable data upon receipt of the communication and presented to the user. The user can send a request for an additional fragment of the message if needed to complete the message or to decipher the message.

System and method of protecting digitally transferred data

Growing community of inventors

Poughkeepsie, NY, United States of America

Jie Zheng