Globalfoundries Singapore Pte. Ltd.

Globalfoundries U.S. Inc.

Applied Materials, Inc.

Jie Zeng

Kyong Jin Hwang

Raunak Kumar

Milova Paul

Sagar Premnath Karalkar

Souvick Mitra

Robert J Gauthier, Jr

Robert Jan Visser

Arvind Sundarrajan

Guan Huei See

Prerna Sonthalia Goradia

Chai Ean Gill

Prayudi Lianto

Ranga Rao Arnepalli

Prantik Mahajan

James Jerry Joseph

Ajay Ajay

Ting Yang

The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge devices and methods of manufacture. The structure includes: a semiconductor material including an emitter region, a base region adjacent to the emitter region; and a collector region; a thermally grown insulator region on the semiconductor material extending from the base region to the collector region; and a field plate on the thermally grown insulator region and overlapping with the base region.

High-voltage electrostatic discharge device

Disclosed is a semiconductor structure including a device (e.g., a bi-directional semiconductor-controlled rectifier, such as a bi-directional silicon-controlled rectifier (BDSCR)) and, within the device, at least two dual-level isolation structures. Each dual-level isolation structure includes a first section at the top surface of the semiconductor substrate and one or more second sections extending through the first section deeper into the semiconductor substrate. The dual-level isolation structures are positioned within the device so as to increase well resistance. By increasing well resistance, the trigger voltage of the device can be reduced without increasing device size. Also disclosed is a method of forming dual-level isolation structures within such a device.

Bi-directional semiconductor-controlled rectifier with dual-level isolation structures and method

The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge devices and methods of manufacture. The structure includes: a semiconductor material comprising an emitter region, a base region, and a collector region; a thermally grown insulator region on the semiconductor material which extends over a junction of the base region and the collector region; a first field plate on the thermally grown insulator region, the first field plate being electrically connected to the emitter region; and a second field plate on the thermally grown insulator region, the second field plate being electrically connected to the collector region.

Disclosed is a semiconductor structure including a semiconductor substrate (e.g., a P-substrate) and a symmetric BDSCR. The BDSCR includes, within the substrate, a first well (e.g., a low-doped deep Nwell) and, within the first well, symmetric side sections and a middle section positioned laterally between the side sections. Each side section includes: second and third wells (e.g., Pwells), where the third well is shallower than and has a higher conductivity level than the second well. Each middle section includes multiple floating wells including: two fourth wells (e.g., Nwells), which have a higher conductivity level than the first well, and a fifth well (e.g., another Pwell), which is positioned laterally between and shallower than the fourth wells. By incorporating the floating wells into the middle section, high current tolerance is improved.

Symmetric bi-directional silicon-controlled rectifier for electrostatic discharge protection

The present disclosure relates to semiconductor structures and, more particularly, to improved turn-on voltage of high voltage electrostatic discharge device and methods of manufacture. The structure comprises a high voltage NPN with polysilicon material on an isolation structure located at a base region, the polysilicon material extending to at least one of a collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.

High voltage electrostatic devices

An electrostatic discharge (ESD) protection device including: a substrate including: a first, second and third doped regions, the second doped region disposed between the first and third doped regions, the second doped region has a first conductivity type and a first doping concentration and the first and third doped regions have a second conductivity type and a second doping concentration; first and second doped terminal regions disposed within the first and second doped regions, respectively; and a doped island region disposed within the second doped region, the first and second doped terminal regions and doped island region have the second conductivity type and a third doping concentration, the third doping concentration higher than the first and second doping concentrations; and conductive terminals respectively coupled to the doped terminal regions; and an insulation layer arranged on the substrate between the conductive terminals and covering at least the second doped region.

Bi-directional bi-polar device for ESD protection

Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure includes a first well and a second well in a semiconductor substrate. The first well has a first conductivity type, and the second well has a second conductivity type opposite to the first conductivity type. The structure further includes a first terminal having a doped region that has a portion in the first well, and a second terminal including a second doped region that has a portion in the first well and a third doped region in the second well. The first and second doped regions have the second conductivity type, the third doped region has the first conductivity type, and the second doped region is positioned in a lateral direction between the first doped region and the third doped region.

Silicon-controlled rectifiers for electrostatic discharge protection

An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, an active region, a first terminal region, and a second terminal region. The substrate includes dopants having a first dopant conductivity. The active region is arranged over the substrate and has an upper surface. The first terminal region and the second terminal region are arranged in the active region laterally spaced apart from each other. The first terminal region and the second terminal region each include a well region having dopants of the first dopant conductivity and a first doped region arranged in the well region. The first doped region includes dopants having a second dopant conductivity.

Electrostatic discharge protection devices for bi-directional current protection

Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure includes first and second wells in the semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite to the first conductivity type. First and second conductor layers are positioned on the semiconductor substrate. The first conductor layer partially overlaps with the first well, and the second conductor layer partially overlaps with the second well. A third doped region, which has the second conductivity type, is laterally positioned in the semiconductor substrate between the first and second conductor layers.

Silicon-controlled rectifiers for an electrostatic discharge protection device

An ESD protection device may include a substrate having first and second substrate layers, and first and second bridged regions. Each substrate layer may include first and second border regions and a middle region laterally therebetween. Each bridged region may be arranged within the middle region and a respective border region of the second substrate layer. The middle region of the second substrate layer may be laterally narrower than the middle region of the first substrate layer. Each border region of the second substrate layer may be partially arranged over the middle region of the first substrate layer and partially arranged over a respective border region of the first substrate layer. The border regions of the substrate layers, and the bridged regions may have a first conductivity type, and the middle regions of the substrate layers may have a second conductivity type different from the first conductivity type.

Electrostatic discharge protection devices and methods for fabricating electrostatic discharge protection devices

An electrostatic discharge (ESD) protection device may be provided, including a substrate having a conductivity region arranged therein, a first terminal region and a second terminal region arranged within the conductivity region, and a field distribution structure. The field distribution structure may include an intermediate region arranged within the conductivity region between the first terminal region and the second terminal region, an isolation element arranged over the intermediate region, and a first conductive plate and a second conductive plate arranged over the isolation element. The first conductive plate may be electrically connected to the first terminal region and the second conductive plate may be electrically connected to the second terminal region.

Electrostatic discharge protection devices and methods of forming electrostatic discharge protection devices

A semiconductor device includes a substrate; a collector including a buried layer within the substrate, a first well region over a first portion of the buried layer, and a first conductivity region at least partially within the first well region; a base including a second well region over a second portion of the buried layer and laterally adjacent to the first well region, and a second conductivity region at least partially within the second well region; an emitter including a third conductivity region at least partially within the second conductivity region; an isolation element between the first and the third conductivity regions; a conductive plate on the isolation element and electrically connected with the first conductivity region. The buried layer, the first well region, the first and the third conductivity regions have a first conductivity type; the second well region and the second conductivity region have a second conductivity type.

Semiconductor device and method of forming the same

An ESD protection device may include a substrate, a first conductivity region arranged at least partially within the substrate, a second conductivity region arranged at least partially within the first conductivity region, third and fourth conductivity regions arranged at least partially within the second conductivity region, and first and second terminal portions arranged at least partially within the third and fourth conductivity regions respectively. The third and fourth conductivity regions may be spaced apart from each other. The substrate and the second conductivity region may have a first conductivity type. The first conductivity region, third conductivity region, fourth conductivity region and first and second terminal portions may have a second conductivity type different from the first conductivity type. The first and second terminal portions may have higher doping concentrations than the third and fourth conductivity regions respectively.

Electrostatic discharge protection device

Integrated circuits including an electrostatic discharge device and methods of forming the integrated circuits are provided herein. In an embodiment, an integrated circuit includes an n-type epitaxy layer, a segmented p-well, a p-type buried layer, and a collector region. The segmented p-well is formed in the n-type epitaxy layer. The segmented p-well defines and laterally surrounds a spacing region of the n-type epitaxy layer. The p-type buried layer is formed in the spacing region. The p-type buried layer laterally extends into the segmented p-well about the spacing region and impedes current flow between an underlying portion of the n-type epitaxy layer in relation to the p-type buried layer and an overlying portion of the n-type epitaxy layer in the spacing region. The collector region of the electrostatic discharge device is formed in the overlying portion of the n-type epitaxy layer in the spacing region.

Integrated circuits including an electrostatic discharge device and methods of producing the same

The present disclosure generally relates to semiconductor structures and, more particularly, to electrostatic discharge protective structures and methods of manufacture. The structure includes: an epitaxial layer comprising a first region, a second region and a third region; a plurality of gate structures connecting the first region to the second region and the second region to the third region; and a plurality of terminals connected to the first region and the third region and the gate structures.

Growing community of inventors

Singapore, Singapore

Jie Zeng