International Business Machines Corporation

Jie Yang

Kangguo Cheng

Peng Xu

Shogo Mochizuki

Zhenxing Bi

Praneet Adusumilli

Zuoguang Liu

Chun Wing Yeung

Chi-Chun Liu

Tenko Yamashita

Chen Zhang

Dexin Kong

A neural network device comprises a first plurality of synapse network capacitors, wherein the synapse network capacitors of the first plurality of synapse network capacitors share a first output terminal. The neural network device further comprises a second plurality of synapse network capacitors, wherein the synapse network capacitors of the second plurality of synapse network capacitors share a second output terminal. Still further, the neural network device comprises a metal shielding disposed between the first output terminal and the second output terminal. The neural network device may be used as part of an artificial intelligence system.

Capacitor-based synapse network structure with metal shielding between outputs

A semiconductor device includes gate structures formed transversely over semiconductor fins on a substrate. The gate material includes a gate conductor and a dielectric cap on the gate conductor. The device further includes unipolar spacers formed over the gate structures only. The semiconductor fins are free from the unipolar spacers, and the unipolar spacers have a substantially uniform thickness vertically along the gate structures and include a spacer material with an etch selectivity greater than SiN for oxide removal.

Unipolar spacer formation for finFETs

A method of forming complementary vertical fins and vertical fins with uniform heights, including, forming a trench in a region of a substrate, wherein the trench extends through an upper portion of the substrate and a buried punch-through stop layer, and extends into a lower portion of the substrate, forming a reformed punch-through stop layer in a bottom portion of the trench, forming a fin formation region on the reformed punch-through stop layer, and forming a complementary vertical fin from the fin formation region and a vertical fin from the upper portion of the substrate on a first region of the substrate adjacent to the second region.

Fabrication of fin field effect transistor complementary metal-oxide-semiconductor devices with uniform hybrid channels

A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a source/drain region with a first material on the fins, a first cap layer with a second material over the source/drain region, and a second cap layer with a third material on the first cap layer. A dielectric layer is deposited over the second cap layer. The sacrificial gate stack is removed to expose a channel region of the fins. A gate stack is formed over the channel region of the fins. A portion of the dielectric layer is removed to expose the second cap layer. The second cap layer and the first cap layer are removed to expose the source/drain region. A conductive material is deposited on the source/drain region.

Sacrificial cap for forming semiconductor contact

A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

Dual channel FinFETs having uniform fin heights

A method for forming a semiconductor device includes forming a strained fin on a substrate, a sacrificial gate on a channel region of the fin, a first spacer adjacent to a sidewall of the fin, and a second spacer adjacent to the first spacer. A source/drain region is grown on an exposed portion of the fin. Atoms are driven from the source/drain region into the fin and form an oxide layer on the source/drain region. The second spacer and the oxide layer are removed. An insulator layer is formed over the source/drain region, and the sacrificial gate is removed to expose the channel region of the fin. A gate stack is formed over the channel region of the fin.

Forming strained channel with germanium condensation

A semiconductor device includes a semiconductor fin arranged on a substrate, a gate stack arranged over a channel region of the fin, and a spacer arranged adjacent to the gate stack. A source/drain region is arranged in the fin the source/drain region having a cavity that exposes a portion of the semiconductor fin. An insulator layer is arranged over a portion of the fin, and a conductive contact material is arranged in the cavity and over portions of the source/drain region.

Semiconductor device with increased source/drain area

A method for forming a spacer for a semiconductor device includes patterning gate material in a transverse orientation relative to semiconductor fins formed on a substrate and conformally depositing a dummy spacer layer over surfaces of gate structures and the fins. A dielectric fill formed over the gate structures and the fins is planarized to remove a portion of the dummy spacer layer formed on tops of the gate structures and expose the dummy spacer layer at tops of the sidewalls of the gate structures. Channels are formed by removing the dummy spacer layer along the sidewalls of the gate structures. The fins are protected by the dielectric fill. A spacer is formed by filling the channels with a spacer material. The dielectric fill and the dummy spacer layer are removed to expose the fins. Source and drain regions are formed between the gate structures on the fins.

A semiconductor device includes semiconductor fins formed on a substrate, gate structures formed transversely over the fins, unipolar spacers formed over the gate structures only, and source and drain regions formed between the gate structures on the fins. The fins are free from the unipolar spacers, and the unipolar spacers have a substantially uniform thickness vertically along the gate structures and include a spacer material with an etch selectivity greater than SiN for oxide removal.

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Clifton Park, NY, United States of America

Jie Yang