Cisco Technology, Inc.

Jie Xue

Zhiping Yang

Li Li

Yida Zou

ShiJie Wen

Mudasir Ahmad

Mohan R Nagar

Kuo-Chuan Liu

Bangalore J Shanker

Jovica Savic

Kenneth Hubbard

Dao-I Tony Lin

Anthony Winston

James Edwin Turman

D Brice Achkir

Xinli Gu

Shobhana Punjabi

Jonathan M Parlan

Andy Yu

Pierre Chor-Fung Chia

Nandakumar Krishnan

Zoe Frances Conroy

An approach is presented herein to use an in-situ algorithmic decision methodology during each stage of testing before 2C/4C to decide how long to test, how much margin should be used for each device under the test (DUT) to shorten or eliminate 2C/4C testing. Each DUT will be tested differently based on the risk level or the likelihood of failure at 2C/4C. To be able to achieve this, low-level hardware (HW) based sensors (on the printed circuit board assembly (PCBA), in power module, in silicon components, in silicon component complex, etc.) are used to collect telemetry data with a high frequency data acquisition rate during the testing. As testing is ongoing for each DUT, a margin distribution and algorithm modeling is performed in-situ.

Telemetry-based model driven manufacturing test methodology

A multi-layer substrate stacking a plurality of insulating substrates supports one or more devices. Each substrate includes a face supporting conductive traces and edges surrounding the face at a substantially perpendicular angle. The multi-layer substrate includes a ground plane on a first substrate and a power plane on a second substrate. The ground plane is connected to at least one ground pad disposed on a first edge of the first substrate, which provides a low inductance ground path to the ground plane. The power plane is connected to at least one power pad disposed on a second edge of the second substrate, which provides a low inductance power path to the power plane.

Optimized power delivery for multi-layer substrate

A method, computer system, and computer program product are provided for stress-testing electronics using telemetry modeling. Telemetry data is received from one or more devices under test during a hardware testing phase, the telemetry data including one or more telemetry parameters. The telemetry data is processed using a predictive model to determine future values for the one or more telemetry parameters. Additional hardware testing is performed, wherein the additional hardware testing includes adjusting one or more testing components based on the determined future values.

Stress-testing electrical components using telemetry modeling

An apparatus includes a cavity formed in a support structure, the support structure being operable to support a semiconductor device. A circuit element is disposed in the cavity in the support structure, and the cavity in the support structure is filled with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material. The semiconductor device is electrically connected to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

Semiconductor package including an embedded circuit component within a support structure of the package

A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

Manufacturing a semiconductor package including an embedded circuit component within a support structure of the package

A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.

Method and apparatus for supporting a computer chip on a printed circuit board assembly

Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.

Techniques for embedded memory self repair

In one embodiment, the reliability of the L2 power and/or ground sub-arrays of contacts of a functional integrated circuit device is verified by applying a reference voltage to a selected contact in sub-array and sequentially measuring the voltage at other contacts in the sub-array. If the voltage levels are greater than a threshold voltage level then the functional integrated circuit device is verified as being reliable.

Monitoring of interconnect reliability using a programmable device

An area array device has a grid array of primary electrical contacts coupled to a coupling surface of the device and configured to carry data signals between the area array package and a circuit board. The area array device also has an additional series of secondary electrical contacts coupled to the coupling surface of the device and configured to carry power signals between the area array package and the circuit board. The additional series of secondary electrical contacts provides a relatively large amount of power to the area array package while allowing a manufacturer to maintain the number of primary electrical contacts of the grid array configured to carrying data signals and therefore maintain the overall performance of the area array package.

Methods and apparatus for providing a power signal to an area array package

A circuit board component includes a substrate having non-conductive material and conductive material supported by the non-conductive material. The conductive material defines a circuit board interface, a die interface, a heat spreader interface, and (iv) a set of connections which interconnects the circuit board interface, the die interface and the heat spreader interface. The component further includes a die coupled to the die interface. The die includes integrated circuitry which is configured to electrically communicate with a circuit board when the circuit board couples to the circuit board interface. The component further includes a heat spreader coupled to the heat spreader interface. The heat spreader is configured to dissipate heat from the die. The heat spreader in combination with the heat spreader interface forms an electromagnetic interference shield when a portion of the circuit board interface connects to a ground reference of the circuit board.

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San Ramon, CA, United States of America

Jie Xue