Mediatek Corporation

International Business Machines Corporation

Jie-Wei Lai

Robert Bogdan Staszewski

Meng-Hsiung Hung

Scott Kevin Reynolds

Brian Allan Floyd

Arun Sridhar Natarajan

Jing-Hong Conan Zhan

Alberto Valdes-Garcia

Sean Timothy Nicolson

Ping-Yu Chen

Ming-Da Tsai

Min Hao Chen

Yuan-Hung Chung

Yang-Chuan Chen

Ming-Dai Tsai

A phased-array receiver that may be effectively implemented on a silicon substrate. A receiver includes multiple radio frequency (RF) front-ends, each configured to receive a signal with a given delay relative to the others such that the gain of the received signal is highest in a given direction. The receiver also includes a power combination network configured to accept an RF signal from each of the RF front-ends and to pass a combined RF signal to a down-conversion element, where the power distribution network includes a combination of active and passive components. Each RF front-end includes a phase shifter configured to delay the signal in accordance with the given direction and a variable amplifier configured to adjust the gain of the signal.

Phased-array transceiver for millimeter-wave frequencies

A digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.

Digitally-controlled power amplifier with bandpass filtering/transient waveform control and related digitally-controlled power amplifier cell

A transformer power splitter has a plurality of output ports and an input port. The transformer power splitter includes a plurality of primary winding conductors and a plurality of secondary winding conductors. The secondary winding conductors are electrically connected to the output ports respectively. Each of the secondary winding conductors is electrically connected between a positive terminal and a negative terminal of a corresponding output port. The primary winding conductors are magnetically coupled to the secondary winding conductors respectively. The primary winding conductors are configured in a topology including series and parallel connections between a positive terminal and a negative terminal of the input port.

Transformer power splitter having primary winding conductors magnetically coupled to secondary winding conductors and configured in topology including series connection and parallel connection

A transformer power combiner includes a plurality of current combiners and a voltage combiner. The current combiners are coupled in series, and include a plurality of primary winding conductors magnetically coupled to a plurality of secondary winding conductors respectively. Each of the current combiners is configured to combine currents flowing therethrough. The voltage combiner is coupled to a series connection of the current combiners, and is configured to combine voltages across the current combiners to thereby generate an output of the transformer power combiner.

Transformer power combiner having a plurality of current combiners coupled in series and a voltage combiner coupled to a series connection of the current combiners

A digitally-controlled power amplifier (DPA) with bandpass filtering includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.

A digital signal processing circuit includes a combining stage and an output stage. The combining stage is arranged to receive a plurality of non-overlapping clock signals having a same frequency but different phases, receive a plurality of first input bit streams, and generate a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals. The output stage is arranged to generate an output according to the first output bit stream. A digital signal processing method includes: receiving a plurality of non-overlapping clock signals having a same frequency but different phases; receiving a plurality of first input bit streams; generating a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals; and generating an output according to the first output bit stream.

Digital signal processing circuit for generating output signal according to non-overlapping clock signals and input bit streams and related wireless communication transmitters

A transmitter includes a power amplifier (PA) and a direct current (DC) voltage tuning circuit. The PA is arranged for receiving a radio-frequency (RF) clock derived from a clock source, and producing an output signal according to at least the RF clock. The DC voltage tuning circuit is arranged for tuning at least one DC voltage supplied to the PA for pulling mitigation of the clock source. A method of pulling mitigation of a source clock by a power amplifier (PA) includes adjusting a direct current (DC) voltage supplied to the PA.

Transmitter employing pulling mitigation mechanism and related method thereof

A transformer-based circuit has at least a first port and a plurality of second ports. The transformer-based circuit includes a first winding conductor and a plurality of second winding conductors. The first winding conductor is electrically connected to the first port, and has a plurality of sectors connected in series to thereby form a plurality of loops, where the loops are arranged in a concentric-like fashion. The second winding conductors are magnetically coupled to the first winding conductor; besides, the second winding conductors are electrically connected to the second ports, respectively. Overall layout patterns of the second winding conductors are identical to each other. The first winding conductor acts as one of a primary winding conductor and a secondary winding conductor, and each of the second winding conductors acts as the other of the primary winding conductor and the secondary winding conductor.

Transformer-based circuit with compact and/or symmetrical layout design

A multi-stage digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, a plurality of drivers, and an output stage. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The drivers are coupled to the RF clock, and arranged for producing a plurality of intermediate signals, wherein at least one driver of the drivers is responsive to at least one bit of the digital ACW signal. The output stage is coupled to the intermediate signals, and arranged for producing an output signal.

Multi-stage digitally-controlled power amplifier

A phased-array transmitter and receiver that may be effectively implemented on a silicon substrate. The transmitter distributes to front-ends, and the receiver combines signals from front-ends, using a power distribution/combination tree that employs both passive and active elements. By monitoring the power inputs and outputs, a digital control is able to rapidly provide phase and gain correction information to the front-ends. Such a transmitter/receiver includes a plurality of radio frequency (RF) front-ends and a power splitting/combining network that includes active and passive components configured to distribute signals to/from the front-ends.

A transformer power combiner having a plurality of input ports and an output port is provided. The transformer power combiner includes a plurality of primary winding conductors and a plurality of secondary winding conductors. The primary winding conductors are electrically connected to the input ports, respectively; in addition, each of the primary winding conductors is electrically connected between a positive terminal and a negative terminal of a corresponding input port. The secondary winding conductors are magnetically coupled to the primary winding conductors, respectively. The secondary winding conductors are configured in a topology including series connection and parallel connection between a positive terminal and a negative terminal of the output port.

Transformer power combiner having secondary winding conductors magnetically coupled to primary winding conductors and configured in topology including series connection and parallel connection

A mixer has a controllable load, a signal mixing module, and a controller. The controllable load is controlled by a control signal to change an equivalent load value thereof. The signal mixing module has an output port coupled to the controllable load and an input port coupled to an input signal, and is used for mixing the input signal with a local oscillation signal. The controller is coupled to the controllable load, and is used for generating the control signal to reduce the equivalent load value of the controllable load during switching transients of the local oscillation signal.

Mixer having controllable load with reduced equivalent load value during switching transients of local oscillating signal

An embodiment of a mixer with carrier leakage self-calibrating is disclosed. The mixer comprises a double balanced mixer, a gm stage comprising a first processing unit and a second processing unit, a current duplicating circuit, a capacitor, a controller and a current compensation unit. The current duplicating circuit selects the first processing unit or the second processing unit and duplicates a duplicated current of the selected processing unit to charge the capacitor. The capacitor has a first terminal and a second terminal, wherein the second terminal is grounded and the first terminal receives the duplicated current. The controller determines a charge time of the capacitor to generate a compensation signal, wherein the charge time is the time that the voltage of the capacitor is charged to equal to a reference voltage. The current compensation unit receives the compensation signal to generate a compensation current to the mixer.

Mixer with self-calibrating carrier leakage mechanism

An amplifier circuit for amplifying an input signal to generate an output signal is provided. The amplifier circuit has a stacked main amplifier, a parallel sub-amplifier, and a signal combiner. The stacked main amplifier includes a first amplifier unit for outputting a first amplified signal generated from processing the input signal; and a second amplifier unit for outputting a second amplified signal generated from processing the first amplified signal. The first amplifier unit and the second amplifier unit share bias current. The parallel sub-amplifier is coupled to the stacked main amplifier according to a parallel connection fashion, and outputs a third amplified signal generated from processing the input signal. The signal combiner combines the second amplified signal and the third amplified signal to generate the output signal.

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Taipei, Taiwan

Jie-Wei Lai