Micron Technology Incorporated

Intel Corporation

Intel Ndtm US LLC

Jie Sun

John David Hopkins

Fatma Arzum Simsek-Ege

Hongbin Zhu

Gordon A Haller

Zhenyu Lu

Brian J Cleereman

Haitao Liu

Haisheng Rong

Guangyu Huang

Randy J Koval

Charles H Dennison

Roger W Lindsay

Purnima Narayanan

James Mathew

Merri Lyn Carlson

Prasanna Srinivasan

Jia Hui Ng

H Jim Fulford

Chandra V Mouli

Krishna Kumar Parat

Han Zhao

Brett D Lowe

Minsoo Lee

Srikant Jayanti

Benben Li

Yunjun Ho

Ranjeet Kumar

Zhaoli Sun

John Heck

David Neil Hutchison

Jonathan K Doylend

Woosung Kim

James Matthew

In one embodiment, a distributed feedback laser includes a laser comprising a waveguide, the waveguide having a variable width from a first end to a second end, the laser to generate optical energy of a plurality of lasing wavelengths. Other embodiments are described and claimed.

Multi-wavelength distributed feedback laser

Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Semiconductor devices and methods of fabrication

A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method.

Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure

Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Methods and apparatuses having memory cells including a monolithic semiconductor channel

There is disclosed in one example a communication system, including: a data transmission interface; and a wavelength division multiplexing (WDM) silicon laser source to provide modulated data on a carrier laser via the data transmission interface, the WDM laser including a single laser cavity to generate an internally multiplexed multi-wavelength laser, the single laser cavity including a filter having a first grating period to generate a first wavelength and a second grating period to generate a second wavelength, the second grating period superimposed on the first grating period.

Multi-wavelength laser

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

Integrated structures and methods of forming vertically-stacked memory cells

Embodiments herein relate to photonic integrated circuits with an on-chip optical isolator. A photonic transmitter chip may include a laser and an on-chip isolator optically coupled with the laser that includes an optical waveguide having a section coupled with a magneto-optic liquid phase epitaxy grown garnet film. In some embodiments, a cladding may be coupled with the garnet film, the on-chip isolator may be arranged in a Mach-Zehnder interferometer configuration, the waveguide may include one or more polarization rotators, and/or the garnet film may be formed of a material from a rare-earth garnet family. Other embodiments may be described and/or claimed.

On-chip optical isolator

An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.

Three dimensional NAND flash with self-aligned select gate

A transmission circuit includes an array of subarrays of emitters with quasi-periodic spacing. A first subarray of emitters emits a source signal, and a second subarray of emitters emits the source signal. The first and second subarrays are separated by a subarray spacing that quasi-periodic, wherein the spacing between different subarrays is different. The quasi-periodic subarray spacing is to cause constructive interference of a main lobe of the emissions from the subarrays, and to cause non-constructive interference of sidelobes of the emissions. The spacing between emitters in the subarrays can vary from one subarray to another.

Wide-angle, aliasing-free beam steering using aperiodic emitter arrays

Growing community of inventors

Boise, ID, United States of America

Jie Sun