Omnivision Technologies, Inc.

Rambus Inc.

Altera Corporation

Jie Shen

Wilson Wong

Weiqi Ding

Sangeeta Raman

Howard E Rhodes

Thomas Vogelsang

Brian S Leibowitz

David Wolk Mendel

Tim Tri Hoang

Peng T Li

Tiejun Dai

David Geoffrey Stork

Hae-Chang Lee

Jizhang Shan

Kun-Yung Chang

Thungoc M Tran

James Edward Harris

Farshid Aryanfar

Johannes Solhusvik

Maxim W Smirnov

Min Qu

Wei Li

Yanjing Ke

Ting Wu

Xiong Liu

Yueyong Wang

Song Xue

Xudong Shi

Hyunseok Lee

Yeuyong Wang

Kun-Yang (Ken) Chang

Stacked chip imaging system comprising pixel array partitioned into pixel sub-arrays (PSAs) disposed in first semiconductor die and ADC circuitry including ADC circuits disposed in second semiconductor die. Each PSA is arranged into pixel groups. Each pixel group generates pixel data signals. Pixel array captures image data of first frame with first exposure time, second frame with second exposure time, third frame with third exposure time, and fourth frame with fourth exposure time. First, second, third and fourth exposure times are different. At least one of the pixel groups in each of the pixel sub-arrays is coupled to a different ADC circuit from pixels groups remaining in each of the pixel sub-arrays. ADC circuitry acquires the pixel data signals. For each frame, ADC circuits converts pixel data signal received from pixel groups respectively coupled thereto from analog to digital to generate ADC outputs. Other embodiments are also described.

Method and system of implementing an uneven timing gap between each image capture in an image sensor

A method of detecting light-emitting diode (LED) light starts with a control circuitry generating a shutter signal that is transmitted to a pixel array to control image acquisition by the pixel array and to establish a set exposure time. The readout circuitry may then read out the image data from the pixel array that includes reading out the image data from a plurality of successive and overlapped frames having the set exposure time. The set exposure time may be the same for each of the frames. The successive and overlapped frames may be interlaced frames. Other embodiments are also described.

Method and system to detect a light-emitting diode

An image sensor includes a pixel array disposed in a first semiconductor die. The pixel array is partitioned into a plurality of pixel sub-arrays. Each one of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups. Each one of the plurality of pixel groups is arranged into a p&#xd7;q array of pixel cells. A plurality of readout circuits is disposed in a second semiconductor die. An interconnect layer is stacked between the first semiconductor die and the second semiconductor die. The interconnect layer includes a plurality of conductors. Each one of the plurality of pixel sub-arrays is coupled to a corresponding one of the plurality of readout circuits through a corresponding one of the plurality of conductors.

Stacked chip shared pixel architecture

A floorplan-optimized stacked image sensor and a method for designing the sensor are disclosed. A sensor layer includes multiple PSAs partitioned into PSA groups. A circuit layer includes multiple analog-to-digital converters each communicatively coupled to a different PSA. Each analog-to-digital converter (ADC) is semi-aligned to the PSA group associated with the PSA to which it is communicatively coupled. The floorplan of ADCs maximizes contiguous global-based space on the circuit layer uninterrupted by an ADC. The resulting circuit layer floorplan has one or more global-based spaces interleaved with one or more local-based spaces containing ADCs.

Floorplan-optimized stacked image sensor and associated methods

A system and method for high dynamic range (HDR) imaging includes writing a first, second, and third sub-frame to a memory at a first, second, and third readout time, respectively, the first, second, and third sub-frame being generated by a same first sub-array of the array of image pixels. Subsequent to the third readout time, the first, second, and third sub-frames are sent to an image signal processor. Also subsequent to the third readout time, a fourth sub-frame is sent to the image sensor. The fourth sub-frame is generated by the same first sub-array of the array of image pixels. The fourth sub-frame bypasses the memory by being sent from an analog-to-digital converter to the image signal processor without being written to the memory.

High dynamic range imaging with reduced frame buffer

In an integrated-circuit image sensor, binary sample values are read out from an array of pixels after successive sampling intervals that collectively span an image exposure interval and include at least two sampling intervals of unequal duration. Each pixel of the array is conditionally reset after each of the successive sampling intervals according to whether the pixel yields a binary sample in a first state or a second state.

Image sensor sampled at non-uniform intervals

Readout circuitry to readout an array of image sensor pixels includes readout units that include a plurality of analog-to-digital converters ('ADCs'), a plurality of blocks of Static Random-Access Memory ('SRAM'), and a plurality of blocks of Dynamic Random-Access Memory (&#x201c;DRAM&#x201d;). The plurality ADCs is coupled to readout analog image signals two-dimensional blocks of the array of image sensor pixels. The plurality of blocks of SRAM is coupled to receive digital image signals from the ADCs. The digital image signals are representative of the analog image signal readout from the two-dimensional block of pixels. The plurality of blocks of DRAM is coupled to the blocks of SRAM. Each block of SRAM is coupled to sequentially output the digital image signals to each of the blocks of DRAM. Each of the readout units are coupled to output the digital image signals as a plurality of Input/Output (&#x201c;IO&#x201d;) signals.

Readout circuitry for image sensor

A self-resetting pixel having a memory element to record occurrence of an asynchronous pixel reset and circuitry to enable the memory element to be digitally sampled and cleared is disclosed, together with embodiments of digital image sensors formed by arrays or other collections of such pixels. By marking occurrence of asynchronous reset events within an in-pixel memory element that may be digitally oversampled during an exposure interval (i.e., repeatedly read-out in the form of, for example, a single-bit), it becomes possible to check for and detect asynchronous pixel reset events frequently and efficiently.

Reset-marking pixel sensor

Methods and systems for increasing the effective dynamic range of an image sensor are disclosed. Each pixel in the sensor is exposed for a respective first exposure time. Each pixel's response to the respective first exposure is measured and compared to threshold values. Based on the pixel's response to the respective first exposure time, an optimal exposure is calculated for each pixel. The optimal exposure time is applied to each pixel by utilizing row-enabled and column-enabled signals at each pixel within the sensor.

Increasing dynamic range using multisampling

A system for performing digital correlated double sampling in an image sensor includes a memory for storing most significant bits of the digital image data and reset data produced by an analog-to-digital convertor. The system further includes least significant bit latches for each of the digital image data and reset data. The most significant bits are recombined with the least significant bits in respective recombined latches for each of the digital image data and reset data. A correlated double sampling stage then performs correlated double sampling and stores the correlated double sampled data in memory.

System and method for digital correlated double sampling in an image sensor

A split-counter architecture is implemented within an image sensor system. A first counter within an image sensor region counts image data from pixel regions within the image sensor region, and outputs the most significant bits of the image data to a second counter external to the image sensor region, reducing the bandwidth required between the image sensor region and the second counter, and reducing the size of the counters within the image sensor region.

Image sensor with a split-counter architecture

A measurement circuit includes a phase detection circuit and delay circuitry. The phase detection circuit compares a first signal to a second signal to generate a first phase difference when the delay circuitry generates the second signal based on the first signal. The phase detection circuit compares the first signal to the second signal to generate a second phase difference when the delay circuitry generates the second signal based on a third signal provided to a signal network. The measurement circuit determines a delay of the signal network based on the first and second phase differences.

Techniques to determine signal timing

A method of equalizing an input data signal using a multiple-stage continuous-time linear equalization (CTLE) circuit. A zero-forcing least-mean-square (ZF LMS) procedure is applied to adapt the settings of the CTLE stages. The amplitude settings and the frequency boost settings of the CTLE stages are adapted within the ZF LMS procedure. In an exemplary implementation, an error screening threshold may be applied to an error signal within the ZF LMS procedure to generate a reduced error signal such that weight updates do not occur if the error signal is below the error screening threshold. In addition, if an accumulated sign error signal within the ZF LMS procedure reaches a predetermined maximum indicative of a high loss channel, then a setting for a variable gain amplifier may be increased, and an amplitude setting for the CTLE circuit may be decreased. Other embodiments, aspects and features are also disclosed.

Methods and apparatus for multiple-stage CTLE adaptation

A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.

Techniques for phase detection

The present disclosure provides a floating-tap decision feedback equalization (DFE) circuit. In an exemplary implementation, the floating-tap DFE circuit may include a high-speed shift register, a deserializer and data selector, a bypass deserializer, a high-speed multiplexer and a tap generation circuit. In one aspect of the invention, the floating-tap DFE circuit may advantageously cover an entire tap range beyond a fixed tap range without holes over a range of data rates. Other embodiments, aspects and features are also disclosed.

Growing community of inventors

Fremont, CA, United States of America

Jie Shen