Intel Corporation

Fresco Logic, Inc.

Jie Ni

Rajesh Sankaran Madukkarumukumana

William T Futral

Richard D Reohr, Jr

Brian M Leitner

Dominic J Gasbarro

Richard S Jensen

Tom E Burton

Richard Reohr

Gary A Alvstad

A host controller for a bus is disclosed. The host controller includes a plurality of functional modules interconnected to manage transfer of data between a host bus and a root hub configured to communicate with one or more USB device endpoints on the bus. The plurality of functional modules comprises a DMA engine to transfer one or more data payloads between the host bus and the root hub, a transfer manager configured to determine what control data and/or data payloads should be transferred, and a scheduler to schedule actions performed by the transfer manager. A plurality of control memories, each associated with one or more of the functional modules, store state and/or data information fields accessible by its one or more associated functional modules. The plurality of control memories are distinct and independently accessible from one another.

Multi-port context-based host controller

Provided are a method, system, and article of manufacture, wherein in one implementation of the method a memory buffer is allocated in a host memory by a protocol processor, wherein the host memory is comprised in a host that is coupled to a network adapter. A packet is processed initially at the network adapter to generate data for offloading to the memory buffer in the host. The generated data is offloaded by the protocol processor to the memory buffer in the host. The offloaded data is processed by the protocol processor.

Method, system, and article of manufacture for utilizing host memory from an offload adapter

Machine-readable media, methods, and apparatus are described for transferring data. In some embodiments, an operating system may allocate pages to a buffer and may build a memory descriptor list that references the pages allocated to the buffer. A direct memory access (DMA) controller may process the memory descriptor list and transfer data between a buffer defined by the memory descriptor list and another location per the memory descriptor list. The DMA controller may further support data transfers that involve buffers defined by scatter gather lists and/or chained DMA descriptors built by a device driver.

Direct memory access using memory descriptor list

Apparatus and method for carrying out a DMA transfer wherein an address is written into a DMA register of a DMA controller specifying a memory location within a memory device at which either the parameters for a transfer of a block of data are provided or the status of the transfer of a block of data is to be written by the DMA controller.

Readdressable virtual DMA control and status registers

Provided are a method, system, and article of manufacture, where in one embodiment of the method metadata related to a packet may be allocated in a host memory by a protocol processor, where the host memory may be comprised in a host that may be capable of being coupled to a network adapter. The metadata may be copied from the host memory to an adapter memory that may be associated with the network adapter. The copied metadata may be processed by the protocol processor.

Method, apparatus, system, and article of manufacture for processing control data by an offload adapter

Briefly, in accordance with one embodiment of the invention, a system includes: a network interface unit (NIU). The network interface unit (NIU) is adapted to monitor bandwidth utilization of the netrwork interface unit and adjust the minimum interval for the transmission of a flow control packet, based, at least in part, on the bandwidth utilization determination. Briefly, in accordance with another embodiment of the invention, an apparatus includes at least one integrated circuit. The integrated circuit includes the capability, either alone or in combination with other integrated circuits, to monitor the receive rate utilization of a network interface unit and adjust the minimum interval for the transmission of a flow control frame, based, at least in part, on the receive rate utilization determined.

Network interface unit

Briefly, in accordance with one embodiment of the invention, a method of synchronizing two ends of a bi-directional network communication path includes the following. A sequence of predetermined characters are repeatedly transmitted from an end of a bi-directional network communication path if reception is lost at that end. Synchronization or resynchronization occurs from both ends if the sequence of predetermined characters is received at the other end.

Method and apparatus for synchronizing a network link

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter comprises a host interface arranged to interface a host memory of the host system; a serial interface arranged to receive and transmit data from said switched fabric; a Micro-Engine (ME) arranged to work on multiple tasks based on a Virtual Interface (VI) to support data transfers via the switched fabric, and configured to issue a host request to said host interface for a host transaction including an address and length of host data to be fetched from the host memory, and an End-Of-Cell (EOC) indicator which indicates that a cell has been built for transmission via the serial interface, and to begin working on a different task without waiting for the corresponding host response of the host request from the host interface; a Scheduler arranged to supply a request and a request VI number to said Micro-Engine (ME) for work; and a Request Comparator arranged to check the current VI that is being worked on by the Micro-Engine (ME), and to generate an acknowledgment ACK or a negative acknowledgment NACK to the Scheduler depending upon whether the request VI number is currently being worked on by the Micro-Engine (ME).

Host-fabric adapter and method of connecting a host system to a channel-based switched fabric in a data network

Switch and/or router unit

Briefly, in accordance with one embodiment of the invention, an apparatus includes an integrated circuit that has the capability to schedule transferring processes that have an individual identification number. At least a portion of each individual identification number is used to indicate the presence of each of the transfer processes. Briefly, in accordance with another embodiment of the invention, an integrated circuit having a scheduler of transfer processes, each of the transfer processes having an identification number. The scheduler is coupled to a memory array of bits, and a portion of each identification number is used as a portion of an address to the memory array of bits. Briefly, in accordance with yet another embodiment of the invention, a method of scheduling requests for the transfer of data where each request having an identification number. The identification number is used in addressing a bit in an array of bits and set to indicate the request for the transfer of data.

Method and apparatus for scheduler coupled to memory array wherein scheduler addresses array with at least a portion of an identification number

A network transmitter device and network receiver device is described. The network transmitter device transmits a first voltage potential, a second voltage potential, a third voltage potential and a fourth voltage potential over a first pair of output lines and a second pair of output lines in response to digital signals received over a data input. The network receiver device receives network signals of a first voltage potential, a second voltage potential, a third voltage potential, a fourth voltage potential and a fifth voltage potential over a first pair of output lines and a second pair of output lines. The network receiver device transmits digital signals corresponding to the network signals.

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Portland, OR, United States of America

Jie Ni