Nxp Usa, Inc.

Freescale Semiconductor,inc.

Nxp B.v.

Jie Jin

Jianzhou Wu

Liang Zhang

Yizhong Zhang

Stefano Pietri

Jiawei Fu

Yikun Mo

Michael Todd Berens

Hongyan Yao

Hao Zhi

Zhengxiang Wang

Lei Tian

Chongli Wu

Xiaowen Wu

Xiuqiang Xu

Sitong Wang

Linhao Cao

Shubao Guo

Zhenguo Sun

A self-calibrated buffered-voltage DAC includes a DAC configured to receive an input digital signal and output a first analog voltage signal, a buffer amplifier configured to receive the first voltage signal from the DAC and provide a buffered second analog voltage signal, a voltage to frequency converter configured to selectively receive the first and second voltage signals and provide first and second output signals at respective first and second frequencies, a counter configured to receive the output signals from the voltage to frequency converter and provide respective first and second digital output signals corresponding to the respective first and second frequencies, a comparator configured to receive the first and second digital output signals and provide a digital calibration offset, and a DAC error code module configured to receive a digital input code and the digital calibration offset and to provide an offset corrected input digital signal to the DAC.

Self-calibrating buffered-voltage DAC

A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fbased on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fwith a high frequency clock having a constant frequency f. A memory is included to store at least two counter values generating by comparing fand fonce when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.

Self calibrating digital-to-analog converter

A digital to analog converter (DAC) includes an amplifier including a buffer of the DAC, and a resistor ladder arrangement coupled to a non-inverting input terminal of the amplifier to generate a voltage based on a digital control word. The arrangement includes a first, least-significant bit, segment arranged in one of an R-2R or unit-R configuration, a second, most-significant bit, segment including one or more units each including a second-segment-resistor having a resistor terminal coupled to a respective second switch and having a second resistance, R, and a third segment including one or more third-segment-resistors coupled in parallel to the non-inverting input terminal and connected to a first reference voltage terminal. M2 designates a number of bits in the digital control word for controlling the second switches, and the third segment has a total resistance, Rsp, based on M2.

Digital to analog converter

A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.

Bias current generator circuit

A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.

Current-controlled oscillator with start-up circuit

A method includes selectively communicating each of a plurality of motor winding signals to a first node at an integrated circuit based on whether the corresponding motor winding is energized. A zero-crossing event at an unenergized motor winding signal is determined based the unenergized motor winding signal and based on a signal at the first node.

Zero crossing detection circuit for motor controller and method therefor

A rail-to-rail comparator circuit includes NMOS and PMOS differential input stages with associated loads that are coupled to a shared-load stage. The shared-load stage is coupled to an output stage that includes two active devices. By sharing the load stage between the two input stages, the comparator has a relatively small circuit area, low power draw, and low propagation delay with rail-to-rail input common-mode voltage range.

Rail-to-rail comparator with shared active load

An electrical system can selectively power a load via a USB connection or via another power source, such as a wireless power transfer path. An integrated switch controller determines whether to power the load via the USB connection or the other power sources and controls two external transistors via a single I/O pin connection to implement that determination. The switch controller determines the greater of two voltages: a voltage associated with the USB connection and a voltage associated with the other power source. The switch controller also determines whether there is a valid USB connection. The switch controller circuitry that controls the two external transistors is powered at the greater voltage to ensure that the external transistors are appropriately and securely turned on or off.

Power switch control between USB and wireless power system

A comparator has an input stage having (i) resistor-coupled super source-follower circuits that convert differential input voltages into differential currents and (ii) hysteresis current-injection circuits that inject hysteresis currents into the differential currents. An output stage processes the differential currents to control the comparator output. Common-mode (CM) detection circuits inhibit some of the differential currents from reaching the output stage if the CM voltage is too close to a voltage rail of the comparator. The comparator is able to operate at CM voltages over the entire rail-to-rail range with constant hysteresis voltage.

Rail-to-rail comparator with built-in constant hysteresis

A voltage regulator generates an output voltage that is a designed voltage level below the supply voltage. A reference voltage generator generates a reference voltage between ground and supply voltages. A voltage divider generates a feedback voltage between the supply and output voltages. An amplifier generates an amplifier output voltage based on a difference between the reference and feedback voltages. A buffer buffers the amplifier output voltage. A pass transistor receives the buffered voltage at its control node to sink an average load current appearing at the output node. A capacitor is connected between the supply and output voltages to provide a peak load current. A load-current-detecting transistor receives the buffered voltage at its control node to sense the load current. A compensation transistor compensates for leakage current. An internal load converts the sensed load current into a voltage control signal applied to the compensation transistor.

Supply-side voltage regulator

A low voltage ripple charge pump with slew rate control includes a frequency divider, a clock generator, a current mirror, a switching circuit, a diode network, two capacitors, and a comparator. The frequency divider generates a clock signal from an oscillating signal. The clock generator generates first and second clock signals from the clock signal. The current mirror generates first and second current signals using a reference current. The switching circuit generates first and second voltage signals using the first and second clock signals and the first and second current signals. The comparator generates the oscillating signal based on the first and second voltage signals. The capacitors receive the voltage signals and are connected to the diode network for generating an output signal. The charge pump has low output voltage ripple with small filtering capacitance, which is achieved via slew rate control.

Low voltage ripple charge pump with shared capacitor oscillator

A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.

Trimming circuit for clock source

A CMOS temperature detection circuit includes a start-up circuit for generating a start-up voltage (VN), and a proportional to absolute temperature (PTAT) current generator coupled to the start-up circuit for generating a PTAT current. The start-up voltage turns on the PTAT current generator, and the PTAT current generator uses the sub-threshold characteristics of CMOS to generate the PTAT current. A PTAT voltage generator coupled to the PTAT current generator receives the PTAT current and generates a PTAT voltage and an inverse PTAT voltage (VBE). A comparator circuit coupled to the voltage generator compares the inverse PTAT voltage to first and second alarm limits, which are defined using the generated PTAT voltage, and generates an alarm signal based on the comparison results.

Growing community of inventors

Suzhou, China

Jie Jin