Marvell International Limited

Shanghai Micro Electronics Equipment (group) Co., Ltd.

Shanghai Micro Electronics Equipment Co., Ltd.

Jie Jiang

Yonghua Song

Gang Wang

Tao Shui

Hao Zhou

Song Chen

Shaoyu Wang

Songli Hu

Kai Liu

Dongliang Huang

Jiaozeng Zheng

Haijun Song

Cuixia Tian

Weiwang Sun

Ruzhan Lu

Yichao Shi

Dong Ruan

Chunxia Huang

Jiyuan Mou

Yunbin Pu

Disclosed is a silicon wafer processing device; a pre-aligned optical assembly and an edge exposure assembly are provided on a synchronous bi-directional motion module, reducing the occupied space of the device and saving the installation cost; and furthermore, a synchronous bi-directional motion module, a rotation unit and a position compensation unit on a bottom plate are controlled by means of a control assembly, so as to reduce the operational complexity; and moreover, the synchronous bi-directional motion module is controlled to drive the pre-aligned optical assembly and the edge exposure assembly to simultaneously move, so that the operations of pre-aligning and edge exposure can be performed on silicon wafers of different sizes, thereby saving the switching time and increasing the work efficiency. Further disclosed is a method for processing a silicon wafer using a silicon wafer processing device.

Silicon wafer processing device and method

Disclosed in this invention is a wafer processing apparatus and method for pre-alignment and edge exposure of a wafer. The wafer processing apparatus includes a pre-alignment module, an edge exposure module, a motion module, a control module and a rotary table. The motion module includes a rotation module, a lifting module and a translation module, which are disposed and interconnected above one another. The rotation module is connected at the top to the rotary table and is configured to drive the rotary table to rotate together with the wafer. The lifting module is configured to drive the rotation module and the rotary table to move vertically. The translation module is configured to drive the lifting module and the rotation module to move horizontally. The pre-alignment module and the edge exposure module are positioned in correspondence to opposing sides of the wafer. The invention reduces the number of objects to be controlled as well as the complexity in control and system structure. Additionally, it simplifies the pre-alignment operation and reduces equipment cost.

Wafer processing device and method therefor

An apparatus for pre-aligning a wafer comprises: a wafer stage for carrying the wafer, wherein a first alignment mark (W1) and a second alignment mark (W2) are arranged on the wafer such that they are substantially symmetrical to each other with respect to a center of the wafer; a peripheral vision acquisition system (), configured to perform a first positional compensation for the wafer based on a relative positional relationship of an edge or a notch of the wafer with respect to the wafer stage; and a mark detection system (), configured to capture images of the first and second alignment marks (W1, W2) and perform a second positional compensation for the wafer by determining a relative positional relationship of the center of the wafer with respect to a center of the wafer stage based on the positions of the first and second alignment marks (W1, W2) in a coordinate system of the mark detection system, wherein the coordinate system of the mark detection system () has a horizontal axis (X) defined by a line passing through the center of the wafer stage and a center of the mark detection system () and a vertical axis (Y) defined by a line crossing the horizontal axis (X) at right angles and passing through the center of the wafer stage.

Pre-alignment device and method for wafer

A wafer pre-alignment device is disclosed, including a first unit configured to drive a wafer to rotate or move upward or downward, a second unit configured to drive the wafer to translate, and a position detector including a light source, a lens and an image sensor. A light beam from the light source passes through the wafer and the lens and thereby provides information indicating a position of the wafer to the image sensor. The first unit and the second unit are able to adjust the position of the wafer based on the information obtained by the image sensor. A method for pre-aligning a TSV wafer is also disclosed.

Silicon wafer pre-alignment device and method therefor

A wafer transfer system for use in a photolithography system including a wafer storage apparatus, a pre-alignment apparatus, a buffer stage and a wafer stage is disclosed, which includes: a dual-arm robot, configured to take a wafer to be exposed from the wafer storage apparatus and transfer it onto the pre-alignment apparatus and further configured to remove an exposed wafer from the buffer stage and place it back into the wafer storage apparatus; a wafer-loading linear robot, configured to transfer a pre-aligned wafer onto the wafer stage; and a wafer-unloading linear robot, configured to transfer the exposed wafer onto the buffer stage. The dual-arm robot, the wafer-loading linear robot and the wafer-unloading linear robot can operate in parallel so as to achieve time savings in the wafer transfers.

Silicon wafer transportation system

In one embodiment, an apparatus includes a first supply voltage and a second supply voltage. Level shifter circuitry is configured as a first voltage battery to shift a first voltage and a second voltage battery to shift a second voltage. A first circuit receives the shifted first voltage and sets a third voltage, and receives the shifted second voltage and sets a fourth voltage. The shifted first voltage is greater than the first supply voltage and the shifted second voltage level is less than the second supply voltage. A second circuit sets a fifth voltage and a sixth voltage. The fifth voltage follows the third voltage and the sixth voltage following the fourth voltage.

Voltage reference buffer using voltage battery level shifter

In accordance with the teachings described herein, systems and methods are provided for a time-interleaved pipeline analog to digital converter. An example pipeline analog to digital converter may include passive sampling circuits and a multiplying digital to analog converter circuit. A first passive sampling circuit includes an input terminal coupled to an analog input signal, and outputs a first sample voltage that is responsive to the analog input signal. A second passive sampling circuit includes an input terminal coupled to the analog input signal, and outputs a second sample voltage that is responsive to the analog input signal. The first and second passive sampling circuits are clocked such that the first sample voltage and the second sample voltage are time-interleaved. A multiplying analog to digital converter (MDAC) circuit receives the time-interleaved first and second sample voltages from the first and second passive sampling circuits and processes the time-interleaved first and second sample voltages to generate a residue output voltage.

Low power high speed pipeline ADC

In accordance with the teachings described herein, systems and methods are provided for charge compensation. A system may include an operational transconductance amplifier including an input terminal and an output terminal, a transistor network, and a capacitive circuit. The transistor network may be coupled in a feedback loop between the input terminal and the output terminal. The capacitive circuit may be configured to compensate a charge built on a parasitic capacitance of the transistor network during operation.

Growing community of inventors

Shanghai, China

Jie Jiang