Kabushiki Kaisha Toshiba

Chinese Academy of Sciences

Guangzhou Artificial Intelligence and Advanced Computing Institute of Casia

Guangdong Institute of Artificial Intelligence and Advanced Computing

Jie Hao

Tao Wang

Donglin Wang

Shaolin Xie

Leizu Yin

Jun Liang

Yafang Song

Jian Luan

Qiuxiang Fan

Lin Shu

Xiao Lin

Hui Feng

Pei Ding

Wenqing Hu

Dakun Zhang

Liangtian Zhao

Xiaojun Xue

Kun Yong

Tao Su

Huifeng Zhu

Zhengshan Xue

Lei He

Lifu Yi

Jichong Guo

Zhifeng Lv

Meiting Zhao

Yan Deng

The field of high-speed data acquisition and network data processing, and particularly relates to an Ethernet data stream recording method, an Ethernet data stream recording system, and an Ethernet data stream recording device for a high-speed data acquisition system. It is intended to solve problems such as a low utilization rate of CPU, poor system compatibility, difficulty in packaging and deployment and low reliability of system transmission of the traditional high-speed data acquisition system. The method of the present disclosure includes: isolating a preset number of CPU cores after a Linux operating system is booted; uninstalling a kernel network card driver of the operating system and creating a hugepage memory pool; for each 10-gigabit network card, allocating a corresponding data-receiving buffer pool and a corresponding lock-free FIFO buffer, and initializing a PCIE register of each 10-gigabit network card such that each 10-gigabit network card enters into an acquisition state; and continuously receiving packets acquired by each 10-gigabit network card in a driving manner of user space polling and performing disk recording. According to the present disclosure, the utilization rate of CPU, system compatibility and transmission reliability are improved and the difficulty in packaging and deployment is decreased.

Ethernet data stream recording method and system for high-speed data acquisition system

A method and device for implementing an FPGA-based large-scale radio frequency interference array correlator are provided. The method includes: obtaining the number of channels of data of a radio frequency interference array, and performing average division; calculating the total correlation of data group and the total correlation between the data group and other data groups respectively through corresponding correlation calculation modules, and performing an accumulation calculation in an integration period to complete the total correlation operation of the radio frequency interference array. By means of grouping division and time division multiplexing, the FPGA resource is effectively utilized, and the calculation process of FPGA is simplified. The new method is suitable for the operation process of the system with high parallelism and high real-time requirements, and provides a high-efficiency solution for the real-time calculation of massive data of the large-scale radio frequency interference array.

Method and device for implementing an FPGA-based large-scale radio frequency interference array correlator

A digital receiving apparatus includes an analog-to-digital conversion module, a polyphase filter module, a fast Fourier transform module and a phase compensation module, which transforms signals of a target radio source from time domain to frequency domain. It further includes a standard time acquisition module configured to acquire a standard timestamp, a communication module configured to communicate with a host computer, a delay parameter temporary storage module configured to store a to-be-compensated delay parameter, a control enable module configured to generate an enable signal, a delay module configured to perform delay, and a phase parameter generation module configured to temporarily store the to-be-compensated delay parameter and convert it into a phase compensation parameter. The present invention achieves precise synchronous system startup, and the to-be-compensated parameter is updated and aligned in real time to compensate for a time-varying delay difference to accurately track with precision and observe the target radio source.

Digital receiving apparatus, system, and method for tracking and observing target radio source

According to one embodiment, According to one embodiment, a machine translation apparatus includes a circuitry and a memory. The circuitry is configured to input a sentence of a first language, to segment the sentence to obtain a plurality of phrases, to search a translation model for translation options of a second language of each of the plurality of phrases, and to select top N translation options with high probabilities for decoding. N is an integer equal to or larger than 1. Furthermore, the circuitry is configured to combine the top N translation options of the plurality of phases to obtain a plurality of translation hypotheses, to search user history phrase pairs for the translation hypotheses, and to increase a score of a translation hypothesis existing in the user history phrase pairs. The memory is configured to store the score of the translation hypothesis.

Machine translation method and machine translation apparatus

According to one embodiment, an apparatus for training a neural network acoustic model includes a calculating unit, a clustering unit, and a sharing unit. The calculating unit calculates, based on training data including a training speech and a labeled phoneme state, scores of phoneme states different from the labeled phoneme state. The clustering unit clusters a phoneme state whose score is larger than a predetermined threshold and the labeled phoneme state. The sharing unit shares probability of the labeled phoneme state by the clustered phoneme states. The training unit trains the neural network acoustic model based on the training speech and the clustered phoneme states.

Apparatus and method for training a neural network acoustic model, and speech recognition apparatus and method

According to one aspect, there is provided an apparatus for improving a bilingual corpus including a plurality of sentence pairs of a first language and a second language and word alignment information of each of the sentence pairs, the apparatus comprises: an extracting unit for extracting a split candidate from word alignment information of a given sentence pair; a calculating unit for calculating split confidence of said split candidate; a comparing unit for comparing said split confidence and a pre-set threshold; and a splitting unit for splitting said given sentence pair at said split candidate in a case that said split confidence is larger than said pre-set threshold.

Method and apparatus for improving a bilingual corpus, machine translation method and apparatus

A data access method and device for parallel FFT computation. In the method, FFT data and twiddle factors are stored in multi-granularity parallel memories, and divided into groups throughout the computation flow according to a uniform butterfly representation. Each group of data involves multiple butterflies that support parallel computation. Meanwhile, according to the butterfly representation, it is convenient to generate data address and twiddle factor coefficient address for each group. With different R/W granularities, it is possible to read/write data and corresponding twiddle factors in parallel from the multi-granularity memories. The method and device further provide data access devices for parallel FFT computation. In the method and device, no conflict will occur during read/write operations of memories, and no extract step is required for sorting the read/written data. Further, the method and device can flexibly define the parallel granularity according to particular applications.

Data access method and device for parallel FFT computation

A parallel bit reversal device and method. The device includes a parallel bit reversal unit, a butterfly computation and control unit, and a memory. The butterfly computation and control unit is coupled to the memory via a data bus. The parallel bit reversal unit is configured to bit-reverse butterfly group data used by the butterfly computation and control unit. The parallel bit reversal unit includes an address reversing logic coupled to the butterfly computation and control unit, and configured to perform mirror reversal and right-shift operations on a read address from the butterfly computation and control unit.

Parallel bit reversal devices and methods

A method and device for multi-granularity parallel FFT butterfly computation. The method and device read data and twiddle factors for computation in one butterfly group from the input buffers and the twiddle factor buffer at a time, perform multi-stage butterfly computation in parallel using uniform butterfly representations, and write the results back to the input buffers. The method and device greatly reduce the frequency for accessing the memory, improve speed for butterfly computation, and reduce power consumption. The method and device achieve multi-granularity butterfly computation of various data formats in a parallel and efficient manner. The method and device can specify the parallel granularity and data format for butterfly computation according to particular applications, and are applicable to FFT butterfly computation of balanced and unbalanced groups.

Methods and devices for multi-granularity parallel FFT butterfly computation

A multi-granularity parallel FFT computation device including three memories, a butterfly computation device, a state control unit, a data reversing network and a first selector. The three memories are each a multi-granularity parallel memory, and store butterfly group data and twiddle factors corresponding to the butterfly group data. The butterfly computation device perform computations of a butterfly group based on the butterfly group data outputted from the first selector and the corresponding twiddle factors outputted from one of the memories, and write a computation result back to the other two memories. The device can read butterfly group data and corresponding twiddle factors in parallel from the multi-granularity parallel memories with a specific R/W granularity. No memory conflict will occur in the read operation, and no additional process is required for sorting the read/written data.

Multi-granularity parallel FFT computation device

The present invention provides a method and apparatus for enrollment and evaluation of speaker authentication. The method for enrollment of speaker authentication, comprising: generating a plurality of acoustic feature vector sequences respectively based on a plurality of utterances of the same content spoken by a speaker; generating a reference template from said plurality of acoustic feature vector sequences; generating a corresponding pseudo-impostor feature vector sequence for each of said plurality of acoustic feature vector sequences based on a code book that includes a plurality of codes and their corresponding feature vectors; and selecting an optimal acoustic feature subset based on said plurality of acoustic feature vector sequences, said reference template and said plurality of pseudo-impostor feature vector sequences.

Method and apparatus for enrollment and evaluation of speaker authentification

The present invention provides a method and apparatus for enrollment and verification of speaker authentication. The method for enrollment of speaker authentication, comprising: extracting an acoustic feature vector sequence from an enrollment utterance of a speaker; and generating a speaker template using the acoustic feature vector sequence; wherein said step of extracting an acoustic feature vector sequence comprises: generating a filter-bank for the enrollment utterance of the speaker for filtering locations and energies of formants in the spectrum of the enrollment utterance based on the enrollment utterance; filtering the spectrum of the enrollment utterance by the generated filter-bank; and generating the acoustic feature vector sequence from the filtered enrollment utterance.

Method and apparatus for enrollment and verification of speaker authentication

The present invention provides a method and apparatus for training a duration prediction model, method and apparatus for duration prediction, method and apparatus for speech synthesis. Said method for training a duration prediction model, comprising: generating an initial duration prediction model with a plurality of attributes related to duration prediction and at least part of possible attribute combinations of said plurality of attributes, in which each of said plurality of attributes and said attribute combinations is included as an item; calculating importance of each said item in said duration prediction model; deleting the item having the lowest importance calculated; re-generating a duration prediction model with the remaining items; determining whether said re-generated duration prediction model is an optimal model; and repeating said step of calculating importance and the following steps, if said duration prediction model is determined as not optimal model.

Duration prediction modeling in speech synthesis

The present invention provides a method and apparatus for verification of speaker authentication. A method for verification of speaker authentication, comprising: inputting an utterance containing a password that is spoken by a speaker; extracting an acoustic feature vector sequence from said inputted utterance; DTW-matching said extracted acoustic feature vector sequence and a speaker template enrolled by an enrolled speaker; calculating each of a plurality of local distances between said DTW-matched acoustic feature vector sequence and said speaker template; nonlinear-transforming said each local distance calculated to give more weights on small local distances; calculating a DTW-matching score based on said plurality of local distances nonlinear-transformed; and comparing said matching score with a predefined discriminating threshold to determine whether said inputted utterance is an utterance containing a password spoken by the enrolled speaker.

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Beijing, China

Jie Hao