Realtek Semiconductor Inc.

Jie-Fan Lai

Shih-Hsiung Huang

Chih-Lung Chen

Yu-Chang Chen

Chien-Ming Wu

Sheng-Hsiung Lin

Liang-Wei Huang

Tai-Cheng Lee

Kuo-Sheng Chung

Bi-Ching Huang

Cheng-Hui Wu

Tzu-Hao Hung

An analog-to-digital converter (ADC) device includes an ADC circuitry and a digital slope ADC circuitry. The ADC circuitry is configured to generate first bits and a first voltage according to an input signal. The digital slope ADC circuitry is configured to generate a second voltage at a node according to the first voltage and to gradually adjust the second voltage to generate second bits. After the second bits are generated, the digital slope ADC circuitry is further configured to perform a noise shaping function according to a first residual signal of the node.

Analog to digital converter device and noise shaping digital slope analog to digital converter circuitry

A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes the following steps: controlling the DAC not to receive the output of the quantizer; controlling the SDM to stop receiving signals; inputting a test signal to the DAC; converting the output of the loop filter to a digital signal; comparing the digital signal with a preset value; and adjusting the loop filter according to the result of comparing the digital signal and the preset value.

Correction method and correction circuit for sigma-delta modulator

A correction method and a correction circuit for a sigma-delta modulator (SDM) are disclosed. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC), and the loop filter includes a resonator. The correction circuit includes a memory and a control circuit. The memory stores multiple program instructions. The control circuit executes the program instructions to correct the SDM. The correction procedure of the SDM includes the following steps: inputting a test signal to the SDM; obtaining a signal characteristic value of an output signal of the SDM; and adjusting the resonator according to the signal characteristic value.

This invention discloses a successive approximation register analog-to-digital converter (SAR ADC) and a control circuit thereof. The SAR ADC includes a comparator, a switched-capacitor digital-to-analog converter (DAC), and a control circuit. The switched-capacitor DAC includes a capacitor and a driving circuit that is electrically connected to the capacitor. The driving circuit comprises a P-type MOSFET and an N-type MOSFET, and the gates of the two MOSFETs are not electrically connected. The P-type MOSFET is controlled by a first control signal, and the N-type MOSFET is controlled by a second control signal. The control circuit controls the voltage at one end of the capacitor to switch from a high voltage level to a low voltage level by controlling the rising edge of the first control signal to lead the rising edge of the second control signal.

Successive approximation register analog-to-digital converter and control circuit thereof

A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes: generating a test signal for a frequency to be tested; inputting the test signal to a feedforward circuit that includes at least one adjustable impedance circuit, the test signal being inputted to the SDM through the impedance circuit; calculating an output signal of the SDM to obtain a value of a signal transfer function (STF) of the SDM at the frequency to be tested; and adjusting the impedance circuit.

A pipelined analog-to-digital converter includes: a first switched capacitor network, a first digital-to-analog converter, a second switched capacitor network, a second digital-to-analog converter, and an operational amplifier. The outputs from the first switched capacitor network and the first digital-to-analog converter form a first subtraction signal. The outputs from the second switched capacitor network and the second digital-to-analog converter form a second subtraction signal. The operational amplifier is arranged to operably generate an output signal based on the first subtraction signal or the second subtraction signal, and to operably switch coupling relationship of multiple candidate capacitors of the operational amplifier based on the magnitude of an input signal of a prior stage circuit, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.

Pipelined analog-to-digital converter having operational amplifier shared by different circuit stages

An operational amplifier includes: a first gain stage for generating a second signal based on a first signal transmitted from a prior stage circuit; a second gain stage for generating an output signal based on the second signal; multiple candidate capacitors; and a capacitor selection circuit for switching the coupling relationship of the multiple candidate capacitors based on the magnitude of an input signal of the prior stage circuit, so that only a portion of the multiple candidate capacitors could be coupled to the second gain stage at a time.

Operational amplifier with switchable candidate capacitors

Disclosed is a successive approximation register (SAR) quantizer and a continuous-time sigma-delta modulator (CTSDM) using the SAR quantizer. The SAR quantizer is capable of generating M highly-significant bits as a digital output signal, and generating L lowly-significant bit(s) for the execution of noise shaping operation. Therefore, the SAR quantizer and the CTSDM can reduce the demand for the circuit area of a digital-to-analog converter and lower the delay of a critical path, so as to improve the performance and cut the cost.

Successive approximation register quantizer and continuous-time sigma-delta modulator

A data converter and an impedance matching control method are provided. The data converter includes a comparator, a capacitor array as well as a switch and impedance matching circuit. The comparator includes a first input terminal and a second input terminal. The capacitor array includes a plurality of capacitors, and a first end of each capacitor is coupled to the first input terminal or the second input terminal. The switch and impedance matching circuit is coupled to a second end of a target capacitor among the capacitors and configured to couple the second end to a first reference voltage or a second reference voltage according to a control signal and adjust an impedance according to an impedance adjusting signal, in which the impedance is the impedance of the switch and impedance matching circuit. The first reference voltage is different from the second reference voltage.

Data converter and impedance matching control method thereof

A sample-and-hold amplifier includes: a switched capacitor network for conducting a sample-and-hold operation on an input signal to generate a first signal; and an operational amplifier coupled with the switched capacitor network and including multiple candidate capacitors; wherein the operational amplifier is arranged to operably generate an output signal based on the first signal, and to operably switch coupling relationship of the multiple candidate capacitors based on the magnitude of the input signal, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.

Sample-and-hold amplifier with switchable candidate capacitors

A calibration circuit and calibration method for a successive approximation register analog-to-digital converter (SAR ADC) are disclosed. The SAR ADC includes a comparator and generates a digital code. The calibration method includes the following steps: (a) creating a voltage difference between two inputs of the comparator, with the absolute value of the voltage difference being smaller than or equal to the absolute value of the voltage corresponding to the least significant bit (LSB) of the digital code; (b) updating a count value according to whether a timer of the SAR ADC issues a time-out signal, the timer issuing the time-out signal after a delay time has elapsed; (c) repeating steps (a) through (b) a predetermined number of times; (d) calculating a probability based on the predetermined number of times and the count value; and (e) adjusting the delay time according to the probability.

Calibration circuit and calibration method for successive approximation register analog-to-digital converter

Disclosed is a correcting device of successive approximation analog-to-digital conversion. The correcting device includes a successive approximation register analog-to-digital converter (SAR ADC) and a digital circuit. The SAR ADC is configured to generate a digital output. The digital circuit is configured to determine whether the digital output conforms to a metastable output, and correct the digital output when the digital output conforms to the metastable output. The metastable output is related with a metastable binary comparison-results sequence including successive K comparison results such as 110000 or 001111. The K comparison results include a first comparison result, a second comparison result and successive M comparison results in turn. The first comparison result and the second comparison result are the same; the M comparison results are the same; each of the first comparison result and the second comparison result is different from any of the M comparison results.

Correcting device of successive approximation analog-to-digital conversion

A sigma delta modulator includes an integrator, a quantizer, a randomization circuit, and a digital to analog converter circuit. The integrator is configured to integrate an analog signal, in order to generate a first signal, in which the analog signal is a sum of an input signal and a second signal. The quantizer is coupled to the integrator and configured to quantize the first signal to generate a digital signal which has a plurality of bits. The randomization circuit is coupled to the quantizer, and is configured to randomize partial bits in the plurality of bits of the digital signal, in order to generate first control signals. The digital to analog converter (DAC) circuit is coupled to the quantizer and the randomization circuit, and is configured to generate the second signal according to the first control signals and remaining bits in the plurality of bits of the digital signal.

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Hsinchu, Taiwan

Jie-Fan Lai