Via Technologies, Inc.

Jie Ding

Jiing Lin

Iris Jiang

Fan Yang

Ching-Hsiang Lin

A Dynamic Random Access Memory (DRAM) controller for controlling read and write operations of a DRAM includes a storage unit and a control unit. The storage unit stores a first predetermined size of data including data written into the DRAM in response to a previous partial write request, and stores the corresponding store addresses of the first predetermined size of data in the DRAM. The control unit, in response to a read request, determines whether there exists any address in the store addresses equal to a read address of the read request, and read data corresponding to the read address from the storage unit when there exists same address in the store addresses equal to the read address.

DRAM control method and the DRAM controller utilizing the same

A memory refresh method applicable in a system memory is disclosed. The memory system comprises a plurality of memory ranks. It is to determine whether an access request corresponds to the memory rank, and an idle auto-refresh number of the memory rank is calculated if there is no access request corresponds to the memory rank. The memory rank is switched from an auto-refresh mode to a self-refresh mode when the idle auto-refresh number of the memory rank reaches a predetermined value.

Memory refresh method and system

A method and related apparatus for performing error checking-correcting (ECC). The method divides a memory space provided by a memory into an ECC range and a non-ECC range. When data is read or written, the method determines the address of data is within the ECC range or the non-ECC range so as to decide whether error checking-correcting is performed on the data.

Method and related apparatus for performing error checking-correcting

A method for data error checking includes accessing a plurality of sets of data, each of the sets of data having a plurality of bits; integrating the plurality of sets of data into integral data; generating error checking data according to the integral data, the error checking data being changed following any change of the plurality of sets of data; dividing the error checking data into a plurality of sets of sub-checking data, each set of sub-checking data corresponding to one of the plurality of sets of data; and when transmitting each of the plurality of sets of data in order, transmitting the corresponding sub-checking data in the meantime.

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Taipei, Taiwan

Jie Ding