Taiwan Semiconductor Manufacturing Comp. Ltd.

Jie Chen

Hsien-Wei Chen

Ming-Fa Chen

Ying-Ju Chen

Der-Chyang Yeh

Tsung-Yuan Yu

Chen-Hua Douglas Yu

Sung-Feng Yeh

Hung-Yi Kuo

Hao-Yi Tsai

Ching-Jung Yang

Shin-Puu Jeng

Chi-Hsi Wu

Tung-Liang Shao

Sen-Bor Jan

An-Jhih Su

Tzuan-Horng Liu

Chih-Chia Hu

Sheng-An Kuo

Nien-Fang Wu

Hsien-Wen Liu

A method includes joining a first wafer to a second wafer, forming a first through-via penetrating through the first wafer and further extending into the second wafer, and forming a redistribution line on the first wafer. The redistribution line and the first through-via electrically connect a first conductive feature in the first wafer to a second conductive feature in the second wafer. An electrical connector is formed over the first wafer.

3D stacking architecture through TSV and methods forming same

A semiconductor structure includes a first die and a plurality of first dummy pads. The first die includes a first interconnect structure and a first active pad electrically connected to the first interconnect structure. The first dummy pads laterally surround the first active pad and are electrically floating.

Semiconductor structure

A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

Buffer design for package integration

A package includes an interposer having a first redistribution structure; a first die directly bonded to a first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die directly bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; an encapsulant around the first die and the second die; and a plurality of conductive connectors on a second side of the first redistribution structure opposite to the first die and the second die.

Molded dies in semiconductor packages and methods of forming same

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.

Packages with metal line crack prevention design

A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.

Supporting InFO packages to reduce warpage

A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.

Method for fabricating a chip package

A semiconductor package includes a first die including an optical coupler, a second die disposed on the first die, and a transparent encapsulation material disposed on the first die. The second die includes a substrate and a transparent portion disposed within the substrate and optically coupled to the optical coupler. The transparent encapsulation material extends along sidewalls of the substrate of the second die.

Semiconductor package

A manufacturing method of a semiconductor package includes the following steps. A photonic die is provided, wherein the photonic die includes an optical coupler. An electronic die is bonded over the photonic die. An encapsulating material is provided over the photonic die, wherein the encapsulating material at least laterally encapsulates the electronic die. A substrate is bonded over the encapsulated electronic die. A lens structure is formed over the photonic die, wherein the lens structure is overlapped with the optical coupler from a top view.

Semiconductor package and manufacturing method of semiconductor package

A semiconductor die includes an interconnection structure, conductive pads, a first passivation layer, and a second passivation layer. The conductive pads are disposed over and electrically connected to the interconnection structure. The first passivation layer and the second passivation layer are disposed over the conductive pads. The second passivation layer includes a first portion located between two adjacent conductive pads, and a width of the first portion of the second passivation layer continuously decreases toward the interconnection structure.

Semiconductor die, manufacturing method thereof, and semiconductor package

Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

Structure and method for forming integrated high density MIM capacitor

A semiconductor package includes a die and a plurality of conductive patterns. The die includes a device. The conductive patterns are disposed over the device, wherein the conductive patterns are electrically connected to one another to form a first coil and a second coil surrounding the first coil.

Semiconductor packages

A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.

Semiconductor package and manufacturing method thereof

A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube. The second insulating encapsulant laterally encapsulates the dummy die and the memory cube.

Growing community of inventors

New Taipei, Taiwan

Jie Chen