Peking University

Jibin Zou

Ru Huang

Jiewen Fan

Runsheng Wang

Yangyuan Wang

Yujie Ai

Changze Liu

Xin Huang

Shuai Sun

Gengyu Yang

The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.

Programmable array of silicon nanowire field effect transistor and method for fabricating the same

Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle.

Method for fabricating silicon nanowire field effect transistor based on wet etching

Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes. In the present method, the device requirements are simple, the testing structure is simple, the testing cost is low, the testing is rapid and the trap distribution of the gate dielectric layer of the device can be obtained within a short time, which is suitable for large batches of automatic testing and is especially suitable for process monitoring and finished product quality detection during the manufacture of ultra-small semiconductor devices.

Method for testing density and location of gate dielectric layer trap of semiconductor device

A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges. After that, the following steps are repeated sequentially to form a loop by changing the bias settings: 1) carriers flow into the channel through the source and the drain to form an inversion layer, and a portion of carriers are confined by the traps in the gate dielectric layer; 2) carriers of the inversion layer flow back to the source and the drain respectively, whereas the carriers confined by the traps in the gate dielectric layer do not flow back to the channel; 3) carriers confined by the traps in the gate dielectric layer flow out through the drain terminal only; and the trap density of the gate dielectric layer are calculated according to the period of the loop, the size of the channel of the device, and DC currents at the source and the drain. The method is simple and effective and is easy to setup the instruments with a low cost. The method is applicable to be used in testing traps in the gate dielectric layer of the devices that have no substrate contact, especially the surrounding-gate device.

Method for testing trap density of gate dielectric layer in semiconductor device having no substrate contact

The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Fabrication method of vertical silicon nanowire field effect transistor

The invention provides a high voltage-resistant lateral double-diffused transistor. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s).

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Beijing, China

Jibin Zou