Synopsys, Inc.

Other

Jiayong Le

Mustafa Celik

Ayhan Mutlu

Peivand Tehrani

Duc Huynh

Guy Maor

Li Ding

Lawrence Thomas Pileggi

Xin Liang Li

Feroze P Taraporevala

Xin Wang

Ahmed M Shebaita

Wenwen Chai

Adrian Wrixon

Richard Moloney

Gregory Schulte

Brandon Thompson

Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.

Method to compute timing yield and yield bottleneck using correlated sample generation and efficient statistical simulation

A system receives a circuit description and measures of intrinsic delay, intrinsic delay variation, transition time and transition time variation for each stage and determines stage delay variation of each stage. The system receives a circuit description and derate factors and determines an intrinsic delay standard deviation and a correlation coefficient. The system determines a stage delay variation of each stage based on the determined factors. The system receives parameters describing an asymmetric distribution of delay values and generates a normal distribution of delay values. The system receives measures of nominal transition time at an output and input of a wire, and transition time variation at the input of the wire and determines a transition time variation at the output of the wire. The system receives measures of an Elmore delay and a nominal delay of the wire and determines a delay variation at the output of the wire.

Analyzing delay variations and transition time variations for electronic circuits

An arrival time propagation method and system for statistical circuit analysis that uses a conjugation operation and a negation operation to determine and adjust arrival times in a circuit model and to determine path ordering in a circuit.

Circuit timing analysis

A system and a method are disclosed for performing static timing analysis. Information describing a distorted input waveform is received by a static timing analyzer. A transition time of the distorted input waveform is determined. Based on the determined input transition time a nominal input waveform and a corresponding nominal output waveform are received. An input waveform distortion is computed based on the nominal input waveform and the distorted input waveform. An output waveform distortion is computed based on an augmented circuit and the input waveform distortion. A distorted output waveform is computed based on the nominal output waveform and the output waveform distortion. The waveforms are represented using the distortion values which are smaller than the actual waveform values, thereby allowing for compact representation. A time-shifted version of an uncoupled input waveform is used to perform conservative timing analysis of circuits that accounts for crosstalk in the circuit.

Augmented simulation method for waveform propagation in delay calculation

The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). SCS-OCV introduces complex variation concept to resolve the blocking technical issue of combining local random variations, enabling accurate calculation of statistical variations with correlations, such as common-path pessimism removal (CPPR). SCS-OCV proposes practical statistical min/max operations for random variations that can guarantee pessimism at nominal and targeted N-sigma corner, and extends the method to handle complex variations, enabling graph-based full arrival/required time propagation under variable compaction. SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV. This significantly reduces the learning curve and increases the usage of the technology, being more easily adopted by the industry.

Statistical corner evaluation for complex on-chip variation model

A dual-box location-based on-chip variation (DBLOCV) can be used in STA to significantly reduce pessimism. The DBLOCV analysis includes forming a backward bounding box and a forward bounding box for a cell of the design. A first intermediate maximum distance from the cell to corners of the backward bounding box can be calculated using the coordinates. A second intermediate maximum distance from the cell to corners of the forward bounding box can be calculated using the coordinates. A derate value can be determined from the derate table using the maximum distance of the first and second intermediate maximum distances. STA can be performed using the derate value. At least one timing report can be generated based on the STA.

Dual-box location aware and dual-bitmap voltage domain aware on-chip variation techniques

Statistical corner evaluation for complex on chip variation model

The electrical circuit timing method provides accurate nominal delay together with the delay sensitivities with respect to different circuit elements (e.g., cells, interconnects, etc.) and variational parameters (e.g., process variations; environmental variations). All the sensitivity computations are based on closed-form formulas; as a consequence, the method provides rapidly and at low cost high accuracy and high numerical stability.

Statistical delay and noise calculation considering cell and interconnect variations

Sensitivity-based complex statistical modeling for random on-chip variation

The electrical circuit timing method provides accurate nominal delay together with the delay sensitivities with respect to different circuit elements {e.g., cells, interconnects, etc.) and variational parameters (e.g., process variations; environmental variations). All the sensitivity computations are based on closed-form formulas; as a consequence, the method provides rapidly and at low cost high accuracy and high numerical stability.

The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (). Significant research has been recently focused on developing new statistical timing analysis algorithms (), but often without consideration for how one should interpret the statistical timing results for optimization. The invention provides a sensitivity-based metric () to assess the criticality of each path and/or arc in the statistical timing graph (). The statistical sensitivities for both paths and arcs are defined. It is shown that path sensitivity is equivalent to the probability that a path is critical, and arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability () is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.

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Sunnyvale, CA, United States of America

Jiayong Le